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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id z14-20020a170903018e00b001e088a9e2bcsm1380380plg.292.2024.03.22.02.26.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 02:26:04 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou Subject: [PATCH v2 0/4] Fix fp16 checking in vector fp widen/narrow instructions Date: Fri, 22 Mar 2024 17:25:54 +0800 Message-Id: <20240322092600.1198921-1-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112b; envelope-from=max.chou@sifive.com; helo=mail-yw1-x112b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org When SEW is 16, we need to check whether the Zvfhmin is enabled for the single width operator for vector floating point widen/narrow instructions. The commits in this patchset fix the single width operator checking and remove the redudant SEW checking for vector floating point widen/narrow instructions. v2: Group patchset and rebase to the riscv-to-apply.next branch(commit 385e575) Thanks to those who have already reviewed: Daniel Henrique Barboza dbarboza@ventanamicro.com [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions [PATCH] target/riscv: rvv: Check single width operator for vector fp widen instructions [PATCH] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Max Chou (4): target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions target/riscv: rvv: Check single width operator for vector fp widen instructions target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++--------- 1 file changed, 28 insertions(+), 14 deletions(-)