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Mon, 6 May 2024 11:31:47 -0400 (EDT) From: Jiaxun Yang Subject: [PATCH 0/5] hw/mips: Proper multi core support Date: Mon, 06 May 2024 16:31:34 +0100 Message-Id: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIANb3OGYC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDUwMz3dzMgmLd4twCXcvENMtUc8PEFItkIyWg8oKi1LTMCrBR0bG1tQC V8DEGWgAAAA== To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2782; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=oNlozXeAJRJUSVaV0fKqi4kZN1E3eUjY+6x2UcXdfzA=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjSL7487riTP+lh30eRIuPBRnh87hU5wHr1jM/Wl9T0JI U6O4jnsHaUsDGIcDLJiiiwhAkp9GxovLrj+IOsPzBxWJpAhDFycAjCRZF2G//53D+xfsuI5S+zW Z5/8tDV+6AkeDnl+XFB/Q9enA092d/UyMhx0EjOTSztyeX1LR2Dxvv4dd7fUdqk/kJE6Hlh66P2 dRbwA X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass client-ip=64.147.123.152; envelope-from=jiaxun.yang@flygoat.com; helo=wfhigh1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi all, This series implemented propper multiple core support for MIPS CPS systsm. Previously all CPUs are being implemented as a smt thread in a single core. Now it respects topology supplied in QEMU args. To test: Build a latest kernel with 64r6el_defconfig (tested on 6.6, next-20240506). Then run: ``` qemu-system-mips64el -M boston -cpu I6500 -kernel ~/linux-next/vmlinux -smp 4,cores=2,threads=2 -append "console=ttyS0,115200" -nographic ``` In dmesg of guest kernel: ``` [ 0.000000] VP topology {2,2} total 4 ... [ 0.085190] smp: Bringing up secondary CPUs ... [ 0.090219] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes. [ 0.095461] Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 64 bytes [ 0.096658] CPU1 revision is: 0001b000 (MIPS I6500) [ 0.096718] FPU revision is: 20f30300 [ 0.124711] Synchronize counters for CPU 1: done. [ 0.940979] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes. [ 0.941041] Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 64 bytes [ 0.941256] CPU2 revision is: 0001b000 (MIPS I6500) [ 0.941289] FPU revision is: 20f30300 [ 0.965322] Synchronize counters for CPU 2: done. [ 1.260937] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 bytes. [ 1.261001] Primary data cache 64kB, 4-way, PIPT, no aliases, linesize 64 bytes [ 1.261172] CPU3 revision is: 0001b000 (MIPS I6500) [ 1.261209] FPU revision is: 20f30300 [ 1.285390] Synchronize counters for CPU 3: done. [ 1.346985] smp: Brought up 1 node, 4 CPUs ``` Please review. Thanks To: qemu-devel@nongnu.org Cc: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang --- Jiaxun Yang (5): target/mips: Make globalnumber a CPU property hw/msic/mips_cmgcr: Implement multicore functions hw/msic/mips_cpc: Implement multi core support hw/mips/cps: Implement multi core support hw/mips/boston: Implement multi core support hw/mips/boston.c | 37 +++++++++- hw/mips/cps.c | 66 ++++++++++------- hw/misc/mips_cmgcr.c | 168 +++++++++++++++++++++++++++++++++++-------- hw/misc/mips_cpc.c | 97 ++++++++++++++++++------- include/hw/mips/cps.h | 1 + include/hw/misc/mips_cmgcr.h | 87 +++++++++++++++++++--- include/hw/misc/mips_cpc.h | 15 +++- target/mips/cpu.c | 16 ++++- target/mips/cpu.h | 10 ++- target/mips/sysemu/machine.c | 5 +- 10 files changed, 403 insertions(+), 99 deletions(-) --- base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 change-id: 20240506-mips-smp-9af9e71ad8c2 Best regards,