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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a1781d27bsm301687166b.21.2024.05.11.03.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 May 2024 03:11:02 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, space.monkey.delivers@gmail.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v9 0/6] Pointer Masking update for Zjpm v1.0 Date: Sat, 11 May 2024 13:10:47 +0300 Message-Id: <20240511101053.1875596-1-me@deliversmonkey.space> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Alexey Baturo Hi, It looks like Pointer Masking spec has reached v1.0 and been frozen, rebasing on riscv-to-apply.next branch and resubmitting patches. Thanks. [v8]: Rebasing patches on current qemu branch and resubmitting them. [v7]: I'm terribly sorry, but previous rebase went wrong and somehow I missed it. This time I double-checked rebased version. This patch series is properly rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next [v6]: This patch series is rebased on https://github.com/alistair23/qemu/tree/riscv-to-apply.next [v5]: This patch series targets Zjpm v0.8 extension. The spec itself could be found here: https://github.com/riscv/riscv-j-extension/blob/8088461d8d66a7676872b61c908cbeb7cf5c5d1d/zjpm-spec.pdf This patch series is updated after the suggested comments: - add "x-" to the extension names to indicate experimental [v4]: Patch series updated after the suggested comments: - removed J-letter extension as it's unused - renamed and fixed function to detect if address should be sign-extended - zeroed unused context variables and moved computation logic to another patch - bumped pointer masking version_id and minimum_version_id by 1 [v3]: There patches are updated after Richard's comments: - moved new tb flags to the end - used tcg_gen_(s)extract to get the final address - properly handle CONFIG_USER_ONLY [v2]: As per Richard's suggestion I made pmm field part of tb_flags. It allowed to get rid of global variable to store pmlen. Also it allowed to simplify all the machinery around it. [v1]: It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore. Compared to the original implementation with explicit base and mask CSRs, we now only have several fixed options for number of masked bits which are set using existing CSRs. The changes have been tested with handwritten assembly tests and LLVM HWASAN test suite. Alexey Baturo (6): target/riscv: Remove obsolete pointer masking extension code. target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part of Zjpm v0.8 target/riscv: Add helper functions to calculate current number of masked bits for pointer masking target/riscv: Add pointer masking tb flags target/riscv: Update address modify functions to take into account pointer masking target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension target/riscv/cpu.c | 21 +-- target/riscv/cpu.h | 46 +++-- target/riscv/cpu_bits.h | 90 +--------- target/riscv/cpu_cfg.h | 3 + target/riscv/cpu_helper.c | 97 +++++----- target/riscv/csr.c | 337 ++--------------------------------- target/riscv/machine.c | 20 +-- target/riscv/pmp.c | 13 +- target/riscv/pmp.h | 11 +- target/riscv/tcg/tcg-cpu.c | 5 +- target/riscv/translate.c | 46 ++--- target/riscv/vector_helper.c | 15 +- 12 files changed, 158 insertions(+), 546 deletions(-)