mbox series

[v4,00/14] riscv: QEMU RISC-V IOMMU Support

Message ID 20240624201825.1054980-1-dbarboza@ventanamicro.com (mailing list archive)
Headers show
Series riscv: QEMU RISC-V IOMMU Support | expand

Message

Daniel Henrique Barboza June 24, 2024, 8:18 p.m. UTC 
Hi,

This new version contains changes based on suggestions made during the
v3 review [1]. Most notable changes:

- read/write locks were added in both ctx_lock and iot_lock. This code
  was picked from Tomasz branch;
- a new riscv_iommu_validate_process_ctx() helper was added to make
  process-context validations. Suggested by Jason Chien;
- a new doc patch was added to document how the IOMMU can be used by the
  'virt' RISC-V board. Suggested by Alistair.

Patches based on alistair/riscv-to-apply.next. It's also applicable on
master.

Patches missing reviews/acks: 3, 9, 14

* How it was tested *

This series was tested using an emulated QEMU RISC-V host booting a QEMU
KVM guest, passing through an emulated e1000 network card from the host
to the guest. 

The Linux kernel used for tests can be found here:

https://github.com/tjeznach/linux/tree/riscv_iommu_v6-rc3


Changes from v3:
- patch 3:
  - added FCTL_BE and FCTL_WSI bits to regs_ro[] mask
  - renamed 'ctx->pasid' to 'ctx->process_id'
  - added device translation cache update lock ctx_lock
  - DC.tc.V == 0 is now checked before riscv_iommu_validate_device_ctx()
  - PC.ta.V == 0 now issues a "PDT entry not valid" error in the end of
    riscv_iommu_validate_device_ctx()
  - added a new riscv_iommu_validate_process_ctx() helper to validate PC
    as section 2.2.4 dictates
- patch 5:
  - added RISCV_PCI_CLASS_SYSTEM_IOMMU macro and use it in k->class_id
- patch 8:
  - added update lock iot_lock
- patch 9:
  - added FSC related checks to riscv_iommu_validate_process_ctx()
  - moved 'if (mode == bare)' check to happen after ctx->process_id ==
    noprocid check 
- patch 14 (new):
  - add riscv-iommu docs for more information on how to use the
    riscv-iommu-pci device
- v3 link: https://lore.kernel.org/qemu-riscv/20240523173955.1940072-1-dbarboza@ventanamicro.com/

[1] https://lore.kernel.org/qemu-riscv/20240523173955.1940072-1-dbarboza@ventanamicro.com/


Andrew Jones (1):
  hw/riscv/riscv-iommu: Add another irq for mrif notifications

Daniel Henrique Barboza (4):
  pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
  test/qtest: add riscv-iommu-pci tests
  qtest/riscv-iommu-test: add init queues test
  docs/specs: add riscv-iommu

Tomasz Jeznach (9):
  exec/memtxattr: add process identifier to the transaction attributes
  hw/riscv: add riscv-iommu-bits.h
  hw/riscv: add RISC-V IOMMU base emulation
  hw/riscv: add riscv-iommu-pci reference device
  hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
  hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
  hw/riscv/riscv-iommu: add s-stage and g-stage support
  hw/riscv/riscv-iommu: add ATS support
  hw/riscv/riscv-iommu: add DBG support

 docs/specs/index.rst             |    1 +
 docs/specs/pci-ids.rst           |    2 +
 docs/specs/riscv-iommu.rst       |   55 +
 docs/system/riscv/virt.rst       |   13 +
 hw/riscv/Kconfig                 |    4 +
 hw/riscv/meson.build             |    1 +
 hw/riscv/riscv-iommu-bits.h      |  419 ++++++
 hw/riscv/riscv-iommu-pci.c       |  178 +++
 hw/riscv/riscv-iommu.c           | 2372 ++++++++++++++++++++++++++++++
 hw/riscv/riscv-iommu.h           |  148 ++
 hw/riscv/trace-events            |   15 +
 hw/riscv/trace.h                 |    1 +
 hw/riscv/virt.c                  |   33 +-
 include/exec/memattrs.h          |    5 +
 include/hw/pci/pci.h             |    1 +
 include/hw/riscv/iommu.h         |   36 +
 meson.build                      |    1 +
 tests/qtest/libqos/meson.build   |    4 +
 tests/qtest/libqos/riscv-iommu.c |   76 +
 tests/qtest/libqos/riscv-iommu.h |  100 ++
 tests/qtest/meson.build          |    1 +
 tests/qtest/riscv-iommu-test.c   |  234 +++
 22 files changed, 3699 insertions(+), 1 deletion(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace-events
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 tests/qtest/riscv-iommu-test.c

Comments

Daniel Henrique Barboza July 5, 2024, 9:24 p.m. UTC | #1 
Hi,

Would it make it easier for review if we squash patch 3:

[PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation

and patch 8:

[PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support

In the same patch?

I'm asking because I've been noticing since the first versions that some reviews
on patch 3 seems to refer to context that are s-stage and g-stage related, i.e.
added later. Perhaps squashing them together makes it easier to review since
we'll have a more complete picture. Patch 3 will end up gaining +381 lines
though.



Thanks,

Daniel



On 6/24/24 5:18 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> This new version contains changes based on suggestions made during the
> v3 review [1]. Most notable changes:
> 
> - read/write locks were added in both ctx_lock and iot_lock. This code
>    was picked from Tomasz branch;
> - a new riscv_iommu_validate_process_ctx() helper was added to make
>    process-context validations. Suggested by Jason Chien;
> - a new doc patch was added to document how the IOMMU can be used by the
>    'virt' RISC-V board. Suggested by Alistair.
> 
> Patches based on alistair/riscv-to-apply.next. It's also applicable on
> master.
> 
> Patches missing reviews/acks: 3, 9, 14
> 
> * How it was tested *
> 
> This series was tested using an emulated QEMU RISC-V host booting a QEMU
> KVM guest, passing through an emulated e1000 network card from the host
> to the guest.
> 
> The Linux kernel used for tests can be found here:
> 
> https://github.com/tjeznach/linux/tree/riscv_iommu_v6-rc3
> 
> 
> Changes from v3:
> - patch 3:
>    - added FCTL_BE and FCTL_WSI bits to regs_ro[] mask
>    - renamed 'ctx->pasid' to 'ctx->process_id'
>    - added device translation cache update lock ctx_lock
>    - DC.tc.V == 0 is now checked before riscv_iommu_validate_device_ctx()
>    - PC.ta.V == 0 now issues a "PDT entry not valid" error in the end of
>      riscv_iommu_validate_device_ctx()
>    - added a new riscv_iommu_validate_process_ctx() helper to validate PC
>      as section 2.2.4 dictates
> - patch 5:
>    - added RISCV_PCI_CLASS_SYSTEM_IOMMU macro and use it in k->class_id
> - patch 8:
>    - added update lock iot_lock
> - patch 9:
>    - added FSC related checks to riscv_iommu_validate_process_ctx()
>    - moved 'if (mode == bare)' check to happen after ctx->process_id ==
>      noprocid check
> - patch 14 (new):
>    - add riscv-iommu docs for more information on how to use the
>      riscv-iommu-pci device
> - v3 link: https://lore.kernel.org/qemu-riscv/20240523173955.1940072-1-dbarboza@ventanamicro.com/
> 
> [1] https://lore.kernel.org/qemu-riscv/20240523173955.1940072-1-dbarboza@ventanamicro.com/
> 
> 
> Andrew Jones (1):
>    hw/riscv/riscv-iommu: Add another irq for mrif notifications
> 
> Daniel Henrique Barboza (4):
>    pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
>    test/qtest: add riscv-iommu-pci tests
>    qtest/riscv-iommu-test: add init queues test
>    docs/specs: add riscv-iommu
> 
> Tomasz Jeznach (9):
>    exec/memtxattr: add process identifier to the transaction attributes
>    hw/riscv: add riscv-iommu-bits.h
>    hw/riscv: add RISC-V IOMMU base emulation
>    hw/riscv: add riscv-iommu-pci reference device
>    hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
>    hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
>    hw/riscv/riscv-iommu: add s-stage and g-stage support
>    hw/riscv/riscv-iommu: add ATS support
>    hw/riscv/riscv-iommu: add DBG support
> 
>   docs/specs/index.rst             |    1 +
>   docs/specs/pci-ids.rst           |    2 +
>   docs/specs/riscv-iommu.rst       |   55 +
>   docs/system/riscv/virt.rst       |   13 +
>   hw/riscv/Kconfig                 |    4 +
>   hw/riscv/meson.build             |    1 +
>   hw/riscv/riscv-iommu-bits.h      |  419 ++++++
>   hw/riscv/riscv-iommu-pci.c       |  178 +++
>   hw/riscv/riscv-iommu.c           | 2372 ++++++++++++++++++++++++++++++
>   hw/riscv/riscv-iommu.h           |  148 ++
>   hw/riscv/trace-events            |   15 +
>   hw/riscv/trace.h                 |    1 +
>   hw/riscv/virt.c                  |   33 +-
>   include/exec/memattrs.h          |    5 +
>   include/hw/pci/pci.h             |    1 +
>   include/hw/riscv/iommu.h         |   36 +
>   meson.build                      |    1 +
>   tests/qtest/libqos/meson.build   |    4 +
>   tests/qtest/libqos/riscv-iommu.c |   76 +
>   tests/qtest/libqos/riscv-iommu.h |  100 ++
>   tests/qtest/meson.build          |    1 +
>   tests/qtest/riscv-iommu-test.c   |  234 +++
>   22 files changed, 3699 insertions(+), 1 deletion(-)
>   create mode 100644 docs/specs/riscv-iommu.rst
>   create mode 100644 hw/riscv/riscv-iommu-bits.h
>   create mode 100644 hw/riscv/riscv-iommu-pci.c
>   create mode 100644 hw/riscv/riscv-iommu.c
>   create mode 100644 hw/riscv/riscv-iommu.h
>   create mode 100644 hw/riscv/trace-events
>   create mode 100644 hw/riscv/trace.h
>   create mode 100644 include/hw/riscv/iommu.h
>   create mode 100644 tests/qtest/libqos/riscv-iommu.c
>   create mode 100644 tests/qtest/libqos/riscv-iommu.h
>   create mode 100644 tests/qtest/riscv-iommu-test.c
>
Alistair Francis July 8, 2024, 2:18 a.m. UTC | #2 
On Sat, Jul 6, 2024 at 7:26 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> Would it make it easier for review if we squash patch 3:
>
> [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation
>
> and patch 8:
>
> [PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support
>
> In the same patch?
>
> I'm asking because I've been noticing since the first versions that some reviews
> on patch 3 seems to refer to context that are s-stage and g-stage related, i.e.
> added later. Perhaps squashing them together makes it easier to review since
> we'll have a more complete picture. Patch 3 will end up gaining +381 lines
> though.

Squashing is probably the way to go

Alistair