[00/11,v2] RISC-V: support CLIC v0.9 specification

Message

Ian Brockbank Aug. 19, 2024, 4:02 p.m. UTC

[Resubmission now the merge is correct]

This patch set gives an implementation of "RISC-V Core-Local Interrupt
Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
you can find the pdf format or the source code.

This is based on the implementation from 2021 by Liu Zhiwei [3], who took
over the job from Michael Clark, who gave the first implementation of
clic-v0.7 specification [2]. I believe this implementation addresses all
the comments in Liu Zhiwei's RFC patch thread.

This implementation follows the CLIC 0.9-stable draft at 14 March 2024,
with the following exceptions and implementation details:
 - the CLIC control registers are memory-mapped as per earlier drafts (in
   particular version 0.9-draft, 20 June 2023)
 - the indirect CSR control in 0.9-stable is not implemented
 - the vector table can be either handler addresses (as per the spec)
   or a jump table where each entry is processed as an instruction,
   selectable with version number v0.9-jmp
 - each hart is assigned its own CLIC block
 - if PRV_S and/or PRV_M are supported, they are currently assumed to follow
   the PRV_M registers; a subsequent update will address this
 - support for PRV_S and PRV_M is selectable at CLIC instantiation
 - PRV_S and PRV_U registers are currently separate from PRV_M; a subsequent
   update will turn them into filtered views onto the PRV_M registers
 - each hart is assigned its own CLIC block
 - support for PRV_S and PRV_M is selectable at CLIC instantiation by
   passing in a base address for the given modes; a base address of 0 is
   treated as not supported
 - PRV_S and PRV_U registers are mapped  onto the PRV_M controls with
   appropriate filtering for the access mode
 - the RISCV virt machine has been updated to allow CLIC emulation by
   passing "machine=virt,clic=on" on the command line; various other
   parameters have been added to allow finer control of the CLIC behavior

The implementation (in jump-table mode) has been verified to match the
Cirrus Logic silicon (PRV_M only), which is based upon the Pulp
implementation [4] as of June 2023.

The implementation also includes a selection of qtests designed to verify
operation in all possible combinations of PRV_M, PRV_S and PRV_U.

[1] specification website: https://github.com/riscv/riscv-fast-interrupt.
[2] Michael Clark origin work:
https://github.com/sifive/riscv-qemu/tree/sifive-clic.
[3] RFC Patch submission by Liu Zhiwei:
https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html
[4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic

Ian Brockbank (11):
    target/riscv: Add CLIC CSR mintstatus
    target/riscv: Update CSR xintthresh in CLIC mode
    hw/intc: Add CLIC device
    target/riscv: Update CSR xie in CLIC mode
    target/riscv: Update CSR xip in CLIC mode
    target/riscv: Update CSR xtvec in CLIC mode
    target/riscv: Update CSR xnxti in CLIC mode
    target/riscv: Update interrupt handling in CLIC mode
    target/riscv: Update interrupt return in CLIC mode
    hw/riscv: add CLIC into virt machine
    tests: add riscv clic qtest case and a function in qtest

This message and any attachments may contain privileged and confidential information that is intended solely for the person(s) to whom it is addressed. If you are not an intended recipient you must not: read; copy; distribute; discuss; take any action in or make any reliance upon the contents of this message; nor open or read any attachment. If you have received this message in error, please notify us as soon as possible on the following telephone number and destroy this message including any attachments. Thank you. Cirrus Logic International (UK) Ltd and Cirrus Logic International Semiconductor Ltd are companies registered in Scotland, with registered numbers SC089839 and SC495735 respectively. Our registered office is at 7B Nightingale Way, Quartermile, Edinburgh, EH3 9EG, UK. Tel: [phone]. www.cirrus.com

Comments

Ian Brockbank Sept. 4, 2024, 7:57 a.m. UTC | #1

Hi All,

Has anyone had time to look at this patch set yet? Is there anything I can do to help?

This implements https://wiki.riscv.org/display/HOME/Fast+Interrupts+TG, bringing the draft implementation listed on that page (almost) up to date with v0.9-draft-20240314. The implementation has been verified to match the Cirrus Logic silicon (PRV_M only), which is based upon the Pulp implementation [4] as of June 2023.

How can I help move this forward to get it merged into the mainline?

Thank you,

Ian Brockbank C.Eng.
Senior Staff Software Engineer
Cirrus Logic | cirrus.com | t: [phone] | m: [phone] |@badgertaming


> -----Original Message-----
> From: Ian Brockbank <[e-mail]>
> Sent: Monday, August 19, 2024 5:02 PM
> To: [e-mail]; [e-mail]
> Cc: Palmer Dabbelt <[e-mail]>; Alistair Francis
> <[e-mail]>; Bin Meng <[e-mail]>; Weiwei Li
> <[e-mail]>; Daniel Henrique Barboza
> <[e-mail]>; Liu Zhiwei <[e-mail]>;
> Ian Brockbank <[e-mail]>
> Subject: [PATCH 00/11 v2] RISC-V: support CLIC v0.9 specification
>
> [Resubmission now the merge is correct]
>
> This patch set gives an implementation of "RISC-V Core-Local Interrupt
> Controller(CLIC) Version 0.9-draft-20240314". It comes from [1], where
> you can find the pdf format or the source code.
>
> This is based on the implementation from 2021 by Liu Zhiwei [3], who took
> over the job from Michael Clark, who gave the first implementation of
> clic-v0.7 specification [2]. I believe this implementation addresses all
> the comments in Liu Zhiwei's RFC patch thread.
>
> This implementation follows the CLIC 0.9-stable draft at 14 March 2024,
> with the following exceptions and implementation details:
>  - the CLIC control registers are memory-mapped as per earlier drafts (in
>    particular version 0.9-draft, 20 June 2023)
>  - the indirect CSR control in 0.9-stable is not implemented
>  - the vector table can be either handler addresses (as per the spec)
>    or a jump table where each entry is processed as an instruction,
>    selectable with version number v0.9-jmp
>  - each hart is assigned its own CLIC block
>  - if PRV_S and/or PRV_M are supported, they are currently assumed to
> follow
>    the PRV_M registers; a subsequent update will address this
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation
>  - PRV_S and PRV_U registers are currently separate from PRV_M; a
> subsequent
>    update will turn them into filtered views onto the PRV_M registers
>  - each hart is assigned its own CLIC block
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation by
>    passing in a base address for the given modes; a base address of 0 is
>    treated as not supported
>  - PRV_S and PRV_U registers are mapped  onto the PRV_M controls with
>    appropriate filtering for the access mode
>  - the RISCV virt machine has been updated to allow CLIC emulation by
>    passing "machine=virt,clic=on" on the command line; various other
>    parameters have been added to allow finer control of the CLIC behavior
>
> The implementation (in jump-table mode) has been verified to match the
> Cirrus Logic silicon (PRV_M only), which is based upon the Pulp
> implementation [4] as of June 2023.
>
> The implementation also includes a selection of qtests designed to verify
> operation in all possible combinations of PRV_M, PRV_S and PRV_U.
>
> [1] specification website: https://github.com/riscv/riscv-fast-interrupt.
> [2] Michael Clark origin work:
> https://github.com/sifive/riscv-qemu/tree/sifive-clic.
> [3] RFC Patch submission by Liu Zhiwei:
> https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html
> [4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic
>
> Ian Brockbank (11):
>     target/riscv: Add CLIC CSR mintstatus
>     target/riscv: Update CSR xintthresh in CLIC mode
>     hw/intc: Add CLIC device
>     target/riscv: Update CSR xie in CLIC mode
>     target/riscv: Update CSR xip in CLIC mode
>     target/riscv: Update CSR xtvec in CLIC mode
>     target/riscv: Update CSR xnxti in CLIC mode
>     target/riscv: Update interrupt handling in CLIC mode
>     target/riscv: Update interrupt return in CLIC mode
>     hw/riscv: add CLIC into virt machine
>     tests: add riscv clic qtest case and a function in qtest

This message may contain privileged and/or confidential information. If it appears you received this message in error, please notify us by reply email and then delete the message. Thank you.

Cirrus Logic International (UK) Ltd and Cirrus Logic International Semiconductor Ltd are companies registered in Scotland, with registered numbers SC089839 and SC495735 respectively. Our registered office is at 7B Nightingale Way, Quartermile, Edinburgh, EH3 9EG, UK.

Alistair Francis Sept. 6, 2024, 2:48 a.m. UTC | #2

On Tue, Aug 20, 2024 at 2:08 AM Ian Brockbank <[e-mail]> wrote:
>
> [Resubmission now the merge is correct]
>
> This patch set gives an implementation of "RISC-V Core-Local Interrupt
> Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
> you can find the pdf format or the source code.

Can you please point to the *exact* spec that is used (see below)

>
> This is based on the implementation from 2021 by Liu Zhiwei [3], who took
> over the job from Michael Clark, who gave the first implementation of
> clic-v0.7 specification [2]. I believe this implementation addresses all
> the comments in Liu Zhiwei's RFC patch thread.
>
> This implementation follows the CLIC 0.9-stable draft at 14 March 2024,
> with the following exceptions and implementation details:

I don't follow, the 0.9 spec was released in June

https://github.com/riscv/riscv-fast-interrupt/releases/tag/v0.9

>  - the CLIC control registers are memory-mapped as per earlier drafts (in
>    particular version 0.9-draft, 20 June 2023)

So it's different to the 0.9 spec?

>  - the indirect CSR control in 0.9-stable is not implemented
>  - the vector table can be either handler addresses (as per the spec)
>    or a jump table where each entry is processed as an instruction,
>    selectable with version number v0.9-jmp

We only want to support what is in the spec

Alistair

>  - each hart is assigned its own CLIC block
>  - if PRV_S and/or PRV_M are supported, they are currently assumed to follow
>    the PRV_M registers; a subsequent update will address this
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation
>  - PRV_S and PRV_U registers are currently separate from PRV_M; a subsequent
>    update will turn them into filtered views onto the PRV_M registers
>  - each hart is assigned its own CLIC block
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation by
>    passing in a base address for the given modes; a base address of 0 is
>    treated as not supported
>  - PRV_S and PRV_U registers are mapped  onto the PRV_M controls with
>    appropriate filtering for the access mode
>  - the RISCV virt machine has been updated to allow CLIC emulation by
>    passing "machine=virt,clic=on" on the command line; various other
>    parameters have been added to allow finer control of the CLIC behavior
>
> The implementation (in jump-table mode) has been verified to match the
> Cirrus Logic silicon (PRV_M only), which is based upon the Pulp
> implementation [4] as of June 2023.
>
> The implementation also includes a selection of qtests designed to verify
> operation in all possible combinations of PRV_M, PRV_S and PRV_U.
>
> [1] specification website: https://github.com/riscv/riscv-fast-interrupt.
> [2] Michael Clark origin work:
> https://github.com/sifive/riscv-qemu/tree/sifive-clic.
> [3] RFC Patch submission by Liu Zhiwei:
> https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html
> [4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic
>
> Ian Brockbank (11):
>     target/riscv: Add CLIC CSR mintstatus
>     target/riscv: Update CSR xintthresh in CLIC mode
>     hw/intc: Add CLIC device
>     target/riscv: Update CSR xie in CLIC mode
>     target/riscv: Update CSR xip in CLIC mode
>     target/riscv: Update CSR xtvec in CLIC mode
>     target/riscv: Update CSR xnxti in CLIC mode
>     target/riscv: Update interrupt handling in CLIC mode
>     target/riscv: Update interrupt return in CLIC mode
>     hw/riscv: add CLIC into virt machine
>     tests: add riscv clic qtest case and a function in qtest
>
> This message and any attachments may contain privileged and confidential information that is intended solely for the person(s) to whom it is addressed. If you are not an intended recipient you must not: read; copy; distribute; discuss; take any action in or make any reliance upon the contents of this message; nor open or read any attachment. If you have received this message in error, please notify us as soon as possible on the following telephone number and destroy this message including any attachments. Thank you. Cirrus Logic International (UK) Ltd and Cirrus Logic International Semiconductor Ltd are companies registered in Scotland, with registered numbers SC089839 and SC495735 respectively. Our registered office is at 7B Nightingale Way, Quartermile, Edinburgh, EH3 9EG, UK. Tel: [phone]. www.cirrus.com
>

Alistair Francis Sept. 6, 2024, 3:56 a.m. UTC | #3

On Tue, Aug 20, 2024 at 2:08 AM Ian Brockbank <[e-mail]> wrote:
>
> [Resubmission now the merge is correct]
>
> This patch set gives an implementation of "RISC-V Core-Local Interrupt
> Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where
> you can find the pdf format or the source code.

Thanks for the patches!

I left some comments on the cover letter and throughout the series.

The main points are that we need to support a release spec (draft is
ok, but it needs to be tagged as a version). On top of that we want to
try and keep the CSR changes in target/riscv. We don't want to be
including the hw/intc code all over the place. time_helper.c for
example is how the ACLINT works, where we try to keep as much of the
CPU code in target/riscv.

Also we will need extension checks for all of the relevant CLIC
extensions. Guest code should not notice any changes after this series
unless they enable the CLIC extensions.

Alistair

>
> This is based on the implementation from 2021 by Liu Zhiwei [3], who took
> over the job from Michael Clark, who gave the first implementation of
> clic-v0.7 specification [2]. I believe this implementation addresses all
> the comments in Liu Zhiwei's RFC patch thread.
>
> This implementation follows the CLIC 0.9-stable draft at 14 March 2024,
> with the following exceptions and implementation details:
>  - the CLIC control registers are memory-mapped as per earlier drafts (in
>    particular version 0.9-draft, 20 June 2023)
>  - the indirect CSR control in 0.9-stable is not implemented
>  - the vector table can be either handler addresses (as per the spec)
>    or a jump table where each entry is processed as an instruction,
>    selectable with version number v0.9-jmp
>  - each hart is assigned its own CLIC block
>  - if PRV_S and/or PRV_M are supported, they are currently assumed to follow
>    the PRV_M registers; a subsequent update will address this
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation
>  - PRV_S and PRV_U registers are currently separate from PRV_M; a subsequent
>    update will turn them into filtered views onto the PRV_M registers
>  - each hart is assigned its own CLIC block
>  - support for PRV_S and PRV_M is selectable at CLIC instantiation by
>    passing in a base address for the given modes; a base address of 0 is
>    treated as not supported
>  - PRV_S and PRV_U registers are mapped  onto the PRV_M controls with
>    appropriate filtering for the access mode
>  - the RISCV virt machine has been updated to allow CLIC emulation by
>    passing "machine=virt,clic=on" on the command line; various other
>    parameters have been added to allow finer control of the CLIC behavior
>
> The implementation (in jump-table mode) has been verified to match the
> Cirrus Logic silicon (PRV_M only), which is based upon the Pulp
> implementation [4] as of June 2023.
>
> The implementation also includes a selection of qtests designed to verify
> operation in all possible combinations of PRV_M, PRV_S and PRV_U.
>
> [1] specification website: https://github.com/riscv/riscv-fast-interrupt.
> [2] Michael Clark origin work:
> https://github.com/sifive/riscv-qemu/tree/sifive-clic.
> [3] RFC Patch submission by Liu Zhiwei:
> https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg01417.html
> [4] Pulp implementation of CLIC: https://github.com/pulp-platform/clic
>
> Ian Brockbank (11):
>     target/riscv: Add CLIC CSR mintstatus
>     target/riscv: Update CSR xintthresh in CLIC mode
>     hw/intc: Add CLIC device
>     target/riscv: Update CSR xie in CLIC mode
>     target/riscv: Update CSR xip in CLIC mode
>     target/riscv: Update CSR xtvec in CLIC mode
>     target/riscv: Update CSR xnxti in CLIC mode
>     target/riscv: Update interrupt handling in CLIC mode
>     target/riscv: Update interrupt return in CLIC mode
>     hw/riscv: add CLIC into virt machine
>     tests: add riscv clic qtest case and a function in qtest
>
> This message and any attachments may contain privileged and confidential information that is intended solely for the person(s) to whom it is addressed. If you are not an intended recipient you must not: read; copy; distribute; discuss; take any action in or make any reliance upon the contents of this message; nor open or read any attachment. If you have received this message in error, please notify us as soon as possible on the following telephone number and destroy this message including any attachments. Thank you. Cirrus Logic International (UK) Ltd and Cirrus Logic International Semiconductor Ltd are companies registered in Scotland, with registered numbers SC089839 and SC495735 respectively. Our registered office is at 7B Nightingale Way, Quartermile, Edinburgh, EH3 9EG, UK. Tel: [phone]. www.cirrus.com
>