mbox series

[v4,00/17] intel_iommu: Enable stage-1 translation for emulated device

Message ID 20240930092631.2997543-1-zhenzhong.duan@intel.com (mailing list archive)
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Series intel_iommu: Enable stage-1 translation for emulated device | expand

Message

Duan, Zhenzhong Sept. 30, 2024, 9:26 a.m. UTC 
Hi,

Per Jason Wang's suggestion, iommufd nesting series[1] is split into
"Enable stage-1 translation for emulated device" series and
"Enable stage-1 translation for passthrough device" series.

This series enables stage-1 translation support for emulated device
in intel iommu which we called "modern" mode.

PATCH1-5:  Some preparing work before support stage-1 translation
PATCH6-8:  Implement stage-1 translation for emulated device
PATCH9-13: Emulate iotlb invalidation of stage-1 mapping
PATCH14:   Set default aw_bits to 48 in scalable modren mode
PATCH15-16:Expose scalable modern mode "x-fls" and "fs1gp" to cmdline
PATCH17:   Add qtest

Note in spec revision 3.4, it renames "First-level" to "First-stage",
"Second-level" to "Second-stage". But the scalable mode was added
before that change. So we keep old favor using First-level/fl/Second-level/sl
in code but change to use stage-1/stage-2 in commit log.
But keep in mind First-level/fl/stage-1 all have same meaning,
same for Second-level/sl/stage-2.

Qemu code can be found at [2]
The whole nesting series can be found at [3]

[1] https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html
[2] https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_stage1_emu_v4
[3] https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_nesting_rfcv2

Thanks
Zhenzhong

Changelog:
v4:
- s/Scalable legacy/Scalable in logging (Clement)
- test the mode first to make the intention clearer (Clement)
- s/x-cap-fs1gp/fs1gp and s/VTD_FL_RW_MASK/VTD_FL_RW (Jason)
- introduce x-fls instead of updating x-scalable-mode (Jason)
- Refine comment log in patch4 (jason)
- s/tansltion/translation/ and s/VTD_SPTE_RSVD_LEN/VTD_FPTE_RSVD_LEN/ (Liuyi)
- Update the order and naming of VTD_FPTE_PAGE_* (Liuyi)

v3:
- drop unnecessary !(s->ecap & VTD_ECAP_SMTS) (Clement)
- simplify calculation of return value for vtd_iova_fl_check_canonical() (Liuyi)
- make A/D bit setting atomic (Liuyi)
- refine error msg (Clement, Liuyi)

v2:
- check ecap/cap bits instead of s->scalable_modern in vtd_pe_type_check() (Clement)
- declare VTD_ECAP_FLTS/FS1GP after the feature is implemented (Clement)
- define VTD_INV_DESC_PIOTLB_G (Clement)
- make error msg consistent in vtd_process_piotlb_desc() (Clement)
- refine commit log in patch16 (Clement)
- add VTD_ECAP_IR to ECAP_MODERN_FIXED1 (Clement)
- add a knob x-cap-fs1gp to control stage-1 1G paging capability
- collect Clement's R-B

v1:
- define VTD_HOST_AW_AUTO (Clement)
- passing pgtt as a parameter to vtd_update_iotlb (Clement)
- prefix sl_/fl_ to second/first level specific functions (Clement)
- pick reserved bit check from Clement, add his Co-developed-by
- Update test without using libqtest-single.h (Thomas)

rfcv2:
- split from nesting series (Jason)
- merged some commits from Clement
- add qtest (jason)


Clément Mathieu--Drif (4):
  intel_iommu: Check if the input address is canonical
  intel_iommu: Set accessed and dirty bits during first stage
    translation
  intel_iommu: Add an internal API to find an address space with PASID
  intel_iommu: Add support for PASID-based device IOTLB invalidation

Yi Liu (2):
  intel_iommu: Rename slpte to pte
  intel_iommu: Implement stage-1 translation

Yu Zhang (1):
  intel_iommu: Use the latest fault reasons defined by spec

Zhenzhong Duan (10):
  intel_iommu: Make pasid entry type check accurate
  intel_iommu: Add a placeholder variable for scalable modern mode
  intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb
    invalidation
  intel_iommu: Flush stage-1 cache in iotlb invalidation
  intel_iommu: Process PASID-based iotlb invalidation
  intel_iommu: piotlb invalidation should notify unmap
  intel_iommu: Set default aw_bits to 48 in scalable modern mode
  intel_iommu: Introduce a property x-fls for scalable modern mode
  intel_iommu: Introduce a property to control FS1GP cap bit setting
  tests/qtest: Add intel-iommu test

 MAINTAINERS                    |   1 +
 hw/i386/intel_iommu_internal.h |  92 ++++-
 include/hw/i386/intel_iommu.h  |   8 +-
 hw/i386/intel_iommu.c          | 681 +++++++++++++++++++++++++++------
 tests/qtest/intel-iommu-test.c |  65 ++++
 tests/qtest/meson.build        |   1 +
 6 files changed, 716 insertions(+), 132 deletions(-)
 create mode 100644 tests/qtest/intel-iommu-test.c

Comments

Duan, Zhenzhong Oct. 25, 2024, 6:32 a.m. UTC | #1 
Hi All,

Kindly ping, any more comments?

Thanks
Zhenzhong

>-----Original Message-----
>From: Duan, Zhenzhong <zhenzhong.duan@intel.com>
>Sent: Monday, September 30, 2024 5:26 PM
>Subject: [PATCH v4 00/17] intel_iommu: Enable stage-1 translation for emulated
>device
>
>Hi,
>
>Per Jason Wang's suggestion, iommufd nesting series[1] is split into
>"Enable stage-1 translation for emulated device" series and
>"Enable stage-1 translation for passthrough device" series.
>
>This series enables stage-1 translation support for emulated device
>in intel iommu which we called "modern" mode.
>
>PATCH1-5:  Some preparing work before support stage-1 translation
>PATCH6-8:  Implement stage-1 translation for emulated device
>PATCH9-13: Emulate iotlb invalidation of stage-1 mapping
>PATCH14:   Set default aw_bits to 48 in scalable modren mode
>PATCH15-16:Expose scalable modern mode "x-fls" and "fs1gp" to cmdline
>PATCH17:   Add qtest
>
>Note in spec revision 3.4, it renames "First-level" to "First-stage",
>"Second-level" to "Second-stage". But the scalable mode was added
>before that change. So we keep old favor using First-level/fl/Second-level/sl
>in code but change to use stage-1/stage-2 in commit log.
>But keep in mind First-level/fl/stage-1 all have same meaning,
>same for Second-level/sl/stage-2.
>
>Qemu code can be found at [2]
>The whole nesting series can be found at [3]
>
>[1] https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html
>[2]
>https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_stage1_emu_v4
>[3] https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_nesting_rfcv2
>
>Thanks
>Zhenzhong
>
>Changelog:
>v4:
>- s/Scalable legacy/Scalable in logging (Clement)
>- test the mode first to make the intention clearer (Clement)
>- s/x-cap-fs1gp/fs1gp and s/VTD_FL_RW_MASK/VTD_FL_RW (Jason)
>- introduce x-fls instead of updating x-scalable-mode (Jason)
>- Refine comment log in patch4 (jason)
>- s/tansltion/translation/ and s/VTD_SPTE_RSVD_LEN/VTD_FPTE_RSVD_LEN/
>(Liuyi)
>- Update the order and naming of VTD_FPTE_PAGE_* (Liuyi)
>
>v3:
>- drop unnecessary !(s->ecap & VTD_ECAP_SMTS) (Clement)
>- simplify calculation of return value for vtd_iova_fl_check_canonical() (Liuyi)
>- make A/D bit setting atomic (Liuyi)
>- refine error msg (Clement, Liuyi)
>
>v2:
>- check ecap/cap bits instead of s->scalable_modern in vtd_pe_type_check()
>(Clement)
>- declare VTD_ECAP_FLTS/FS1GP after the feature is implemented (Clement)
>- define VTD_INV_DESC_PIOTLB_G (Clement)
>- make error msg consistent in vtd_process_piotlb_desc() (Clement)
>- refine commit log in patch16 (Clement)
>- add VTD_ECAP_IR to ECAP_MODERN_FIXED1 (Clement)
>- add a knob x-cap-fs1gp to control stage-1 1G paging capability
>- collect Clement's R-B
>
>v1:
>- define VTD_HOST_AW_AUTO (Clement)
>- passing pgtt as a parameter to vtd_update_iotlb (Clement)
>- prefix sl_/fl_ to second/first level specific functions (Clement)
>- pick reserved bit check from Clement, add his Co-developed-by
>- Update test without using libqtest-single.h (Thomas)
>
>rfcv2:
>- split from nesting series (Jason)
>- merged some commits from Clement
>- add qtest (jason)
>
>
>Clément Mathieu--Drif (4):
>  intel_iommu: Check if the input address is canonical
>  intel_iommu: Set accessed and dirty bits during first stage
>    translation
>  intel_iommu: Add an internal API to find an address space with PASID
>  intel_iommu: Add support for PASID-based device IOTLB invalidation
>
>Yi Liu (2):
>  intel_iommu: Rename slpte to pte
>  intel_iommu: Implement stage-1 translation
>
>Yu Zhang (1):
>  intel_iommu: Use the latest fault reasons defined by spec
>
>Zhenzhong Duan (10):
>  intel_iommu: Make pasid entry type check accurate
>  intel_iommu: Add a placeholder variable for scalable modern mode
>  intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb
>    invalidation
>  intel_iommu: Flush stage-1 cache in iotlb invalidation
>  intel_iommu: Process PASID-based iotlb invalidation
>  intel_iommu: piotlb invalidation should notify unmap
>  intel_iommu: Set default aw_bits to 48 in scalable modern mode
>  intel_iommu: Introduce a property x-fls for scalable modern mode
>  intel_iommu: Introduce a property to control FS1GP cap bit setting
>  tests/qtest: Add intel-iommu test
>
> MAINTAINERS                    |   1 +
> hw/i386/intel_iommu_internal.h |  92 ++++-
> include/hw/i386/intel_iommu.h  |   8 +-
> hw/i386/intel_iommu.c          | 681 +++++++++++++++++++++++++++------
> tests/qtest/intel-iommu-test.c |  65 ++++
> tests/qtest/meson.build        |   1 +
> 6 files changed, 716 insertions(+), 132 deletions(-)
> create mode 100644 tests/qtest/intel-iommu-test.c
>
>--
>2.34.1