Message ID | 20241212130422.69380-1-zhiw@nvidia.com (mailing list archive) |
---|---|
Headers | show |
Series | Introduce CXL type-2 device emulation | expand |
On 12/12/24 13:04, Zhi Wang wrote: > Hi folks: > > Per the discussion with Ira/Jonathan in the LPC 2024 and in the CXL > discord channel, we are trying to introduce a CXL type-2 device emulation > in QEMU, as there are work currently on supporting CXL type-2 device [1] > in Linux kernel and CXL type-2 device virtualization [2]. > > It provides a bare minimum base for folks who would like to: > > - Contribute and test the CXL type-2 device support in the linux kernel > and CXL type-2 virtualization without having an actual HW. > - Introduce more emulated features to prototype the kernel CXL type-2 > device features and CXL type-2 virtualization. > > To test this patchset, please refer to steps in [3]. Use this patcheset > with the latest QEMU repo to be the QEMU host. It achieves the same output > as in the demo video [4]: The VFIO CXL core and VFIO CXL sample variant > driver can be attached to the emulated device in the L1 guest and assigned > to the L2 guest. The sample driver in the L2 guest can attach to the > pass-thrued device and create the CXL region. > > Tested on the CXL type-2 virtualization RFC patches [3] with an extra > fix [5]. > > [1] https://lore.kernel.org/linux-cxl/20241209185429.54054-1-alejandro.lucero-palau@amd.com/T/#t > [2] https://www.youtube.com/watch?v=e5OW1pR84Zs > [3] https://lore.kernel.org/kvm/20240920223446.1908673-3-zhiw@nvidia.com/T/ > [4] https://youtu.be/zlk_ecX9bxs?si=pf9CttcGT5KwUgiH > [5] https://lore.kernel.org/linux-cxl/20241212123959.68514-1-zhiw@nvidia.com/T/#u > > Zhi Wang (3): > hw/cxl: factor out cxl_host_addr_to_dpa() > hw/cxl: introduce cxl_component_update_dvsec() > hw/cxl: introduce CXL type-2 device emulation > > MAINTAINERS | 1 + > docs/system/devices/cxl.rst | 11 ++ > hw/cxl/cxl-component-utils.c | 103 ++++++++++- > hw/cxl/cxl-host.c | 19 +- > hw/mem/Kconfig | 5 + > hw/mem/cxl_accel.c | 319 +++++++++++++++++++++++++++++++++ > hw/mem/cxl_type3.c | 61 +------ > hw/mem/meson.build | 1 + > include/hw/cxl/cxl_component.h | 7 + > include/hw/cxl/cxl_device.h | 25 +++ > include/hw/pci/pci_ids.h | 1 + > 11 files changed, 484 insertions(+), 69 deletions(-) > create mode 100644 hw/mem/cxl_accel.c > Hi Zhi, Thank you for this patchset. I have a similar work done for helping in the Type2 support work, but it is all quick-and-dirty changes. My main concern here is with the optional features for Type2: how to create an easy way for configuring Type2 devices using some qemu cxl param. I'm afraid I did not work on that so no suggestions at all! Thank you