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[v2,00/23] target/loongarch: LoongArch32 fixes 1

Message ID 20241226-la32-fixes1-v2-0-0414594f8cb5@flygoat.com (mailing list archive)
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Series target/loongarch: LoongArch32 fixes 1 | expand

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Jiaxun Yang Dec. 26, 2024, 9:19 p.m. UTC 
Hi all,

It's boxing day so time to dump big stuff!

This series is a collection of small fixes I made to TCG for
getting LoongArch32 build to work.

There are still many thing broken, especially on CSRs. More
series following. A brief todo would be:
- Refactoring CSR handling to perform sign extention and handle RO
  fields.
- Refectoring TLB code to allow MTLB only configuration as well as
  special TLBELO format for LA32.
- Check instruction availability for LA32R.
- Handle LA32R priviliged modifications.

LoongArch maintainers, feel free to take subsets as most patches
in this series don't have dependency on each other, and I don't
want to take a pile of patches time by time.

There is a checkpatch error in trans_vec.c.inc inherited from
existing code style.

Thanks for revivewing!

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Changes in v2:
- Dump all patches made ready so far.
- Split LLSC patch into two (Richard, philmd)
- Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com

---
Jiaxun Yang (23):
      target/loongarch: Enable rotr.w/rotri.w for LoongArch32
      target/loongarch: Fix address generation for gen_sc
      target/loongarch: Fix PGD CSR for LoongArch32
      target/loongarch: Perform sign extension for IOCSR reads
      target/loongarch: Use target_ulong for iocsrrd helper results
      target/loongarch: Store some uint64_t values as target_ulong
      target/loongarch: Cast address to 64bit before DMW_64_VSEG shift
      target/loongarch: Fix some modifiers for log formatting
      target/loongarch: Use target_ulong for CSR helpers
      target/loongarch: Scrutinise TCG float translation for 32 bit build
      target/loongarch: Scrutinise TCG vector translation for 32 bit build
      target/loongarch: Scrutinise TCG bitops translation for 32 bit build
      target/loongarch: Fix rdtimer on 32bit build
      target/loongarch: Scrutinise TCG arithmetic translation for 32 bit build
      target/loongarch: Fix load type for gen_ll
      target/loongarch: Define address space information for LoongArch32
      target/loongarch: Refactoring is_la64/is_va32 for LoongArch32
      target/loongarch: ifdef out 64 bit CPUs on 32 bit builds
      target/loongarch: Introduce max32 CPU type
      hw/loongarch/virt: Default to max32 CPU for LoongArch 32 build
      qapi/machine: Replace TARGET_LOONGARCH64 with TARGET_LOONGARCH
      target/loongarch: Wire up LoongArch32 Kconfigs
      config: Add loongarch32-softmmu target

 MAINTAINERS                                        |   4 +-
 configs/devices/loongarch32-softmmu/default.mak    |   7 +
 configs/targets/loongarch32-softmmu.mak            |   7 +
 hw/loongarch/Kconfig                               |   2 +-
 hw/loongarch/virt.c                                |   4 +
 qapi/machine-target.json                           |   8 +-
 target/loongarch/Kconfig                           |   3 +
 target/loongarch/cpu-param.h                       |  12 +-
 target/loongarch/cpu.c                             | 194 ++++++++++++++++-----
 target/loongarch/cpu.h                             | 150 ++++++++--------
 target/loongarch/cpu_helper.c                      |   2 +-
 target/loongarch/helper.h                          |  22 +--
 target/loongarch/machine.c                         | 120 ++++++-------
 target/loongarch/tcg/csr_helper.c                  |   2 +-
 target/loongarch/tcg/insn_trans/trans_arith.c.inc  |  25 ++-
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc |   8 +-
 target/loongarch/tcg/insn_trans/trans_bit.c.inc    |  34 ++--
 target/loongarch/tcg/insn_trans/trans_extra.c.inc  |   8 +-
 target/loongarch/tcg/insn_trans/trans_farith.c.inc |  53 +++---
 target/loongarch/tcg/insn_trans/trans_fcmp.c.inc   |  16 +-
 .../loongarch/tcg/insn_trans/trans_fmemory.c.inc   |  34 ++--
 target/loongarch/tcg/insn_trans/trans_fmov.c.inc   |  83 ++++-----
 target/loongarch/tcg/insn_trans/trans_shift.c.inc  |   4 +-
 target/loongarch/tcg/insn_trans/trans_vec.c.inc    |  70 ++++----
 target/loongarch/tcg/iocsr_helper.c                |  20 +--
 target/loongarch/tcg/op_helper.c                   |   4 +-
 target/loongarch/tcg/tlb_helper.c                  |   2 +-
 target/loongarch/tcg/translate.c                   |  11 +-
 28 files changed, 537 insertions(+), 372 deletions(-)
---
base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
change-id: 20241222-la32-fixes1-368cc14d0986

Best regards,