| Message ID | 20250106054336.1878291-1-frank.chang@sifive.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add Smrnmi support | expand |
On Mon, Jan 6, 2025 at 3:46 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ============================================================= > * mnscratch (0x740) > * mnepc (0x741) > * mncause (0x742) > * mnstatus (0x744) > ============================================================= > * mnret: To return from RNMI interrupt/exception handler. > ============================================================= > > RNMI also has higher priority than any other interrupts or exceptions > and cannot be disabled by software. > > RNMI may be used to route to other devices such as Bus Error Unit or > Watchdog Timer in the future. > > The interrupt/exception trap handler addresses of RNMI are > implementation defined. > > If anyone wants to test the patches, we can use the customized OpenSBI[1], > and the customized QEMU[2]. > > We implemented a PoC RNMI trap handler in the customized OpenSBI. > In the customized QEMU, we use the Smrnmi patches and the patch from > Damien Hedde[3]. The patch from Damien Hedde can be used to inject > the RNMI signal with the qmp command. > > [1] https://github.com/TommyWu-fdgkhdkgh/opensbi/tree/dev/twu/master > [2] https://github.com/sifive/qemu/tree/upstream-smrnmi-v12 > [3] https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06232.html > > Test commands : > $ ./build/qemu-system-riscv64 -M virt -cpu rv64,smrnmi=true, > rnmi-interrupt-vector={Offset of the RNMI handler in the customized > OpenSBI.} -m 4G -smp 2 -serial mon:stdio -serial null -nographic > -bios fw_jump.elf -kernel Image -initrd rootfs.cpio > -qmp unix:/tmp/qmp-sock,server,wait=off > > Use qmp command to inject the RNMI. > > Assert RNMI: > $ ./scripts/qmp/qmp-shell /tmp/qmp-sock > (QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi number=0 value=true > > De-assert RNMI: > (QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi number=0 value=false > > Changelog: > > v12 > * Replace TARGET_LONG_BITS with MXL. > * Add log to inform user that Smrnmi is disabled in the 'max' type CPU. > * Rebase to riscv-to-apply.next. > > v11 > * Squash patch 7 into patch 5. > * Remove "DEFINE_PROP_END_OF_LIST()" from "riscv_harts_props[]" for > the upcoming "DEFINE_PROP_END_OF_LIST()" removal. > > v10 > * Disable Smrnmi for the 'max' type CPU. > > v9 > * Add Zicfilp support for Smrnmi. > * Change the existence checks for 'rnmi-interrupt-vector' and > 'rnmi-exception-vector' to use 'num_rnmi_irqvec' and 'num_rnmi_excpvec'. > * Add warn_once messages for cases where the user sets > 'rnmi-interrupt-vector' or 'rnmi-exception-vector' property without > enabling Smrnmi. > > v8 > * Set virt to false when trapping to M-mode by RNMI. > (Thanks to Clément for the suggestions.) > > v7 > * Rename 'nmi_execp' to 'nnmi_excep' and refactor RNMI exception > checking codes. > (Thanks to Clément for the suggestions.) > * Add the missing REQUIRE_SMRNMI() check and remove the redundant > check in 'helper_mnret'. > * Rebase to riscv-to-apply.next. > (Thanks to Alistair for the suggestions.) > > v6 > * Delete the redundant code in 'riscv_cpu_do_interrupt'. > (Thank Alvin for the suggestion.) > * Split the shared code in 'helper_mret' and 'helper_mnret' into a > helper function 'check_ret_from_m_mode'. > (Thank Alistair for the suggestion.) > > v5 > * Move the patch that adds the Smrnmi extension to the last patch. > (Thank Alistair for the suggestion.) > * Implement an M-mode software PoC for this with implemented handlers. > (Thank Andrew Jones for the suggestion.) > * Add a commit message to all patches of the series. > (Thank Andrew Jones for the suggestion.) > > v4 > * Fix some coding style issues. > (Thank Daniel for the suggestions.) > > v3 > * Update to the newest version of Smrnmi extension specification. > > v2 > * split up the series into more commits for convenience of review. > * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. > > Frank Chang (1): > target/riscv: Add Zicfilp support for Smrnmi > > Tommy Wu (5): > target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig > target/riscv: Add Smrnmi CSRs > target/riscv: Handle Smrnmi interrupt and exception > target/riscv: Add Smrnmi mnret instruction > target/riscv: Add Smrnmi cpu extension Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/riscv_hart.c | 41 ++++++++ > include/hw/riscv/riscv_hart.h | 4 + > target/riscv/cpu.c | 18 ++++ > target/riscv/cpu.h | 10 ++ > target/riscv/cpu_bits.h | 24 +++++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/cpu_helper.c | 99 +++++++++++++++++-- > target/riscv/csr.c | 82 +++++++++++++++ > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 + > .../riscv/insn_trans/trans_privileged.c.inc | 20 ++++ > target/riscv/op_helper.c | 54 +++++++++- > target/riscv/tcg/tcg-cpu.c | 9 ++ > 13 files changed, 353 insertions(+), 13 deletions(-) > > -- > 2.34.1 > >
From: Frank Chang <frank.chang@sifive.com> This patchset added support for Smrnmi Extension in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: ============================================================= * mnscratch (0x740) * mnepc (0x741) * mncause (0x742) * mnstatus (0x744) ============================================================= * mnret: To return from RNMI interrupt/exception handler. ============================================================= RNMI also has higher priority than any other interrupts or exceptions and cannot be disabled by software. RNMI may be used to route to other devices such as Bus Error Unit or Watchdog Timer in the future. The interrupt/exception trap handler addresses of RNMI are implementation defined. If anyone wants to test the patches, we can use the customized OpenSBI[1], and the customized QEMU[2]. We implemented a PoC RNMI trap handler in the customized OpenSBI. In the customized QEMU, we use the Smrnmi patches and the patch from Damien Hedde[3]. The patch from Damien Hedde can be used to inject the RNMI signal with the qmp command. [1] https://github.com/TommyWu-fdgkhdkgh/opensbi/tree/dev/twu/master [2] https://github.com/sifive/qemu/tree/upstream-smrnmi-v12 [3] https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06232.html Test commands : $ ./build/qemu-system-riscv64 -M virt -cpu rv64,smrnmi=true, rnmi-interrupt-vector={Offset of the RNMI handler in the customized OpenSBI.} -m 4G -smp 2 -serial mon:stdio -serial null -nographic -bios fw_jump.elf -kernel Image -initrd rootfs.cpio -qmp unix:/tmp/qmp-sock,server,wait=off Use qmp command to inject the RNMI. Assert RNMI: $ ./scripts/qmp/qmp-shell /tmp/qmp-sock (QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi number=0 value=true De-assert RNMI: (QEMU) gpio-set path=/machine/soc0/harts[0] gpio=riscv.cpu.rnmi number=0 value=false Changelog: v12 * Replace TARGET_LONG_BITS with MXL. * Add log to inform user that Smrnmi is disabled in the 'max' type CPU. * Rebase to riscv-to-apply.next. v11 * Squash patch 7 into patch 5. * Remove "DEFINE_PROP_END_OF_LIST()" from "riscv_harts_props[]" for the upcoming "DEFINE_PROP_END_OF_LIST()" removal. v10 * Disable Smrnmi for the 'max' type CPU. v9 * Add Zicfilp support for Smrnmi. * Change the existence checks for 'rnmi-interrupt-vector' and 'rnmi-exception-vector' to use 'num_rnmi_irqvec' and 'num_rnmi_excpvec'. * Add warn_once messages for cases where the user sets 'rnmi-interrupt-vector' or 'rnmi-exception-vector' property without enabling Smrnmi. v8 * Set virt to false when trapping to M-mode by RNMI. (Thanks to Clément for the suggestions.) v7 * Rename 'nmi_execp' to 'nnmi_excep' and refactor RNMI exception checking codes. (Thanks to Clément for the suggestions.) * Add the missing REQUIRE_SMRNMI() check and remove the redundant check in 'helper_mnret'. * Rebase to riscv-to-apply.next. (Thanks to Alistair for the suggestions.) v6 * Delete the redundant code in 'riscv_cpu_do_interrupt'. (Thank Alvin for the suggestion.) * Split the shared code in 'helper_mret' and 'helper_mnret' into a helper function 'check_ret_from_m_mode'. (Thank Alistair for the suggestion.) v5 * Move the patch that adds the Smrnmi extension to the last patch. (Thank Alistair for the suggestion.) * Implement an M-mode software PoC for this with implemented handlers. (Thank Andrew Jones for the suggestion.) * Add a commit message to all patches of the series. (Thank Andrew Jones for the suggestion.) v4 * Fix some coding style issues. (Thank Daniel for the suggestions.) v3 * Update to the newest version of Smrnmi extension specification. v2 * split up the series into more commits for convenience of review. * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. Frank Chang (1): target/riscv: Add Zicfilp support for Smrnmi Tommy Wu (5): target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig target/riscv: Add Smrnmi CSRs target/riscv: Handle Smrnmi interrupt and exception target/riscv: Add Smrnmi mnret instruction target/riscv: Add Smrnmi cpu extension hw/riscv/riscv_hart.c | 41 ++++++++ include/hw/riscv/riscv_hart.h | 4 + target/riscv/cpu.c | 18 ++++ target/riscv/cpu.h | 10 ++ target/riscv/cpu_bits.h | 24 +++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 99 +++++++++++++++++-- target/riscv/csr.c | 82 +++++++++++++++ target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 + .../riscv/insn_trans/trans_privileged.c.inc | 20 ++++ target/riscv/op_helper.c | 54 +++++++++- target/riscv/tcg/tcg-cpu.c | 9 ++ 13 files changed, 353 insertions(+), 13 deletions(-) -- 2.34.1