[RFC,0/1,v1] target/riscv: optimize the memory probing for vector fault-only-first loads.

Message

Paolo Savini Jan. 29, 2025, 2:44 p.m. UTC

This patch aims at optimizing the helper function that emulates the
fault-only-first load instructions of the RISC-V vector extension.

The current patch removes redundant memory probing from the common execution
path where we don't get exceptions.
The previous version of this emulation always probed the memory with an
element-wise loop over the memory area covered by the load operation and updated
the vl parameter with the element index causing the exception (if any exception
happened).

In this patch we do a probe of the whole memory area covered by the load
instruction and only if a flag other than a watchpoint flag is raised we do
the element-wise probing to find the index of the element causing the exception.

As stated in the standard we don't change vl for watchpoints otherwise the
debug watchpoint events might be lost.

Cc: Richard Handerson <[e-mail]>
Cc: Palmer Dabbelt <[e-mail]>
Cc: Alistair Francis <[e-mail]>
Cc: Bin Meng <[e-mail]>
Cc: Weiwei Li <[e-mail]>
Cc: Daniel Henrique Barboza <[e-mail]>
Cc: Liu Zhiwei <[e-mail]>
Cc: Helene Chelin <[e-mail]>
Cc: Nathan Egge <[e-mail]>
Cc: Max Chou <[e-mail]>
Cc: Jeremy Bennett <[e-mail]>
Cc: Craig Blackmore <[e-mail]>

Paolo Savini (1):
  target/riscv: optimize the memory probing for vector fault-only-first
    loads.

 target/riscv/vector_helper.c | 91 ++++++++++++++++++++++--------------
 1 file changed, 56 insertions(+), 35 deletions(-)