[PULL,v2,00/27] tcg patch queue

Message ID	20250217193009.2873875-1-richard.henderson@linaro.org (mailing list archive)
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL v2 00/27] tcg patch queue Date: Mon, 17 Feb 2025 11:29:41 -0800 Message-ID: <20250217193009.2873875-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Series	tcg patch queue \| expand [PULL,v2,00/27] tcg patch queue [PULL,v2,01/27] tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS [PULL,v2,02/27] tcg: Remove TCG_OVERSIZED_GUEST [PULL,v2,03/27] tcg: Drop support for two address registers in gen_ldst [PULL,v2,04/27] tcg: Merge INDEX_op_qemu__{a32,a64}_ [PULL,v2,05/27] tcg/arm: Drop addrhi from prepare_host_addr [PULL,v2,06/27] tcg/i386: Drop addrhi from prepare_host_addr [PULL,v2,07/27] tcg/mips: Drop addrhi from prepare_host_addr [PULL,v2,08/27] tcg/ppc: Drop addrhi from prepare_host_addr [PULL,v2,09/27] tcg: Replace addr{lo, hi}_reg with addr_reg in TCGLabelQemuLdst [PULL,v2,10/27] plugins: Fix qemu_plugin_read_memory_vaddr parameters [PULL,v2,11/27] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page [PULL,v2,12/27] target/loongarch: Use VADDR_PRIx for logging pc_next [PULL,v2,13/27] include/exec: Change vaddr to uintptr_t [PULL,v2,14/27] include/exec: Use uintptr_t in CPUTLBEntry [PULL,v2,15/27] tcg: Introduce the 'z' constraint for a hardware zero register [PULL,v2,16/27] tcg/aarch64: Use 'z' constraint [PULL,v2,17/27] tcg/loongarch64: Use 'z' constraint [PULL,v2,18/27] tcg/mips: Use 'z' constraint [PULL,v2,19/27] tcg/riscv: Use 'z' constraint [PULL,v2,20/27] tcg/sparc64: Use 'z' constraint [PULL,v2,21/27] elfload: Fix alignment when unmapping excess reservation [PULL,v2,22/27] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h [PULL,v2,23/27] target/sparc: Fix register selection for all FTOx and FxTO instructions [PULL,v2,24/27] target/sparc: Fix gdbstub incorrectly handling registers f32-f62 [PULL,v2,25/27] target/sparc: fake UltraSPARC T1 PCR and PIC registers [PULL,v2,26/27] tcg/i386: Use tcg_{high, unsigned}_cond in tcg_out_brcond2 [PULL,v2,27/27] tcg: Remove TCG_TARGET_HAS_{br, set}cond2 from riscv and loongarch64

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20250217193009.2873875-1-richard.henderson@linaro.org (mailing list archive)

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL v2 00/27] tcg patch queue
Date: Mon, 17 Feb 2025 11:29:41 -0800
Message-ID: <20250217193009.2873875-1-richard.henderson@linaro.org>
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Series

tcg patch queue | expand

v2: Fix target/loongarch printf formats for vaddr Include two more reviewed patches. r~