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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43aba532b8dsm55968335e9.14.2025.02.27.06.27.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 06:27:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/3] target/arm: Fix LDRD, STRD atomicity, fault behaviour Date: Thu, 27 Feb 2025 14:27:43 +0000 Message-ID: <20250227142746.1698904-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Our LDRD and STRD implementations have a couple of bugs: * if the LDRD address is 4-aligned and the load crosses a page boundary and the second load faults and the first load was to the base register (as in cases like "ldrd r2, r3, [r2]", then we must not update the base register before taking the fault. Our current implementation does a sequence of "32 bit load; write to Rt; 32-bit load; write to Rt2" so it mishandles this kind of insn. * if the address is 8-aligned the access must be a 64-bit single-copy atomic access, not two 32-bit accesses. This patchseries fixes both of these bugs, and then cleans up an argument to some utility functions that we no longer need after the first two changes. Note for reviewers: please check that I got the MemOp right: I believe that MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN expresses "8-aligned addresses should be 64-bit atomic, 4-aligned addresses should be 32-bit atomic, less-aligned addresses fault" but I'm not sure if I've correctly understood MO_ATOM_SUBALIGN. Thanks to Stu Grossman for reporting the page-boundary-crossing fault bug, which prompted me to look a bit closer at the code and notice that we weren't doing the atomicity right either. thanks -- PMM Peter Maydell (3): target/arm: Correct LDRD atomicity and fault behaviour target/arm: Correct STRD atomicity target/arm: Drop unused address_offset from op_addr_{rr,ri}_post() target/arm/tcg/translate.c | 137 +++++++++++++++++++++++-------------- 1 file changed, 84 insertions(+), 53 deletions(-)