[00/38] hexagon system emu, part 1/3

Message

Brian Cain March 1, 2025, 5:25 a.m. UTC

hexagon architecture system emulation: part 1/3

These patches are also staged in my tree (branch "hex-next"
at https://github.com/quic/qemu/).  After these three patch series, we're
able to run the test suite for minivm [1].  minivm is a hypervisor,
an implementation of the Hexagon Virtual Machine Specification.

[1] https://github.com/quic/hexagonMVM

Brian Cain (38):
  docs: Add hexagon sysemu docs
  docs/system: Add hexagon CPU emulation
  target/hexagon: Add System/Guest register definitions
  target/hexagon: Make gen_exception_end_tb non-static
  target/hexagon: Switch to tag_ignore(), generate via
    get_{user,sys}_tags()
  target/hexagon: Add privilege check, use tag_ignore()
  target/hexagon: Add a placeholder fp exception
  target/hexagon: Add guest, system reg number defs
  target/hexagon: Add guest, system reg number state
  target/hexagon: Add TCG values for sreg, greg
  target/hexagon: Add guest/sys reg writes to DisasContext
  target/hexagon: Add imported macro, attr defs for sysemu
  target/hexagon: Define DCache states
  target/hexagon: Add new macro definitions for sysemu
  target/hexagon: Add handlers for guest/sysreg r/w
  target/hexagon: Add placeholder greg/sreg r/w helpers
  target/hexagon: Add vmstate representation
  target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()
  target/hexagon: Define register fields for system regs
  target/hexagon: Implement do_raise_exception()
  target/hexagon: Add system reg insns
  target/hexagon: Add sysemu TCG overrides
  target/hexagon: Add implicit attributes to sysemu macros
  target/hexagon: Add TCG overrides for int handler insts
  target/hexagon: Add TCG overrides for thread ctl
  target/hexagon: Add TCG overrides for rte, nmi
  target/hexagon: Add sreg_{read,write} helpers
  target/hexagon: Initialize htid, modectl regs
  target/hexagon: Add locks, id, next_PC to state
  target/hexagon: Add a TLB count property
  target/hexagon: Add {TLB,k0}lock, cause code, wait_next_pc
  target/hexagon: Add stubs for modify_ssr/get_exe_mode
  target/hexagon: Add gdb support for sys regs
  target/hexagon: Add initial MMU model
  target/hexagon: Add IRQ events
  target/hexagon: Add clear_wait_mode() definition
  target/hexagon: Define f{S,G}ET_FIELD macros
  target/hexagon: Add hex_interrupts support

 MAINTAINERS                             |   2 +
 docs/devel/hexagon-sys.rst              | 106 +++++
 docs/devel/index-internals.rst          |   1 +
 docs/system/hexagon/cdsp.rst            |  10 +
 docs/system/hexagon/emulation.rst       |  16 +
 docs/system/target-hexagon.rst          | 101 +++++
 docs/system/targets.rst                 |   1 +
 target/hexagon/cpu-param.h              |   4 +
 target/hexagon/cpu.h                    |  75 +++-
 target/hexagon/cpu_bits.h               |  43 ++
 target/hexagon/cpu_helper.h             |  43 ++
 target/hexagon/gen_tcg.h                |   9 +
 target/hexagon/gen_tcg_sys.h            | 103 +++++
 target/hexagon/helper.h                 |  23 +
 target/hexagon/hex_interrupts.h         |  15 +
 target/hexagon/hex_mmu.h                |  30 ++
 target/hexagon/hex_regs.h               | 115 +++++
 target/hexagon/internal.h               |  16 +
 target/hexagon/macros.h                 |  40 +-
 target/hexagon/max.h                    |  26 ++
 target/hexagon/sys_macros.h             | 238 ++++++++++
 target/hexagon/translate.h              |  45 ++
 target/hexagon/attribs_def.h.inc        | 414 ++++++++++++++++--
 target/hexagon/reg_fields_def.h.inc     |  96 ++++
 target/hexagon/arch.c                   |   5 +
 target/hexagon/cpu.c                    |  87 ++++
 target/hexagon/cpu_helper.c             |  91 ++++
 target/hexagon/gdbstub.c                |  45 ++
 target/hexagon/genptr.c                 | 163 +++++++
 target/hexagon/hex_interrupts.c         | 324 ++++++++++++++
 target/hexagon/hex_mmu.c                | 528 ++++++++++++++++++++++
 target/hexagon/machine.c                |  63 +++
 target/hexagon/op_helper.c              | 248 +++++++++++
 target/hexagon/translate.c              |  18 +-
 gdb-xml/hexagon-sys.xml                 | 116 +++++
 target/hexagon/gen_analyze_funcs.py     |  21 +-
 target/hexagon/gen_helper_funcs.py      |  23 +-
 target/hexagon/gen_helper_protos.py     |  23 +-
 target/hexagon/gen_idef_parser_funcs.py |   2 +
 target/hexagon/gen_op_attribs.py        |   2 +-
 target/hexagon/gen_opcodes_def.py       |   5 +-
 target/hexagon/gen_tcg_func_table.py    |  14 +-
 target/hexagon/gen_tcg_funcs.py         |  32 +-
 target/hexagon/hex_common.py            | 189 +++++++-
 target/hexagon/imported/encode_pp.def   | 213 ++++++---
 target/hexagon/imported/macros.def      | 558 ++++++++++++++++++++++++
 target/hexagon/imported/system.idef     | 262 ++++++++++-
 target/hexagon/meson.build              |  17 +-
 48 files changed, 4435 insertions(+), 186 deletions(-)
 create mode 100644 docs/devel/hexagon-sys.rst
 create mode 100644 docs/system/hexagon/cdsp.rst
 create mode 100644 docs/system/hexagon/emulation.rst
 create mode 100644 docs/system/target-hexagon.rst
 create mode 100644 target/hexagon/cpu_helper.h
 create mode 100644 target/hexagon/gen_tcg_sys.h
 create mode 100644 target/hexagon/hex_interrupts.h
 create mode 100644 target/hexagon/hex_mmu.h
 create mode 100644 target/hexagon/max.h
 create mode 100644 target/hexagon/sys_macros.h
 create mode 100644 target/hexagon/cpu_helper.c
 create mode 100644 target/hexagon/hex_interrupts.c
 create mode 100644 target/hexagon/hex_mmu.c
 create mode 100644 target/hexagon/machine.c
 create mode 100644 gdb-xml/hexagon-sys.xml
 mode change 100755 => 100644 target/hexagon/imported/macros.def