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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fea67a5dc8sm4732955a91.23.2025.02.28.21.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 21:28:49 -0800 (PST) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com Subject: [PATCH 00/39] hexagon system emu, part 2/3 Date: Fri, 28 Feb 2025 21:28:06 -0800 Message-Id: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Proofpoint-GUID: VfsebIj21_XwYZGu3BPM6JvuRXU73xdh X-Proofpoint-ORIG-GUID: VfsebIj21_XwYZGu3BPM6JvuRXU73xdh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-01_01,2025-02-28_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=327 mlxscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503010040 Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org hexagon architecture system emulation: part 2/3 This series includes the k0 and TLB locking implementation. This was briefly discussed on-list at https://lists.nongnu.org/archive/html/qemu-devel/2024-01/msg04801.html and perhaps we can continue/follow-up discussion on the relevant patch(es) in this series. Brian Cain (38): target/hexagon: Implement ciad helper target/hexagon: Implement {c,}swi helpers target/hexagon: Implement iassign{r,w} helpers target/hexagon: Implement start/stop helpers target/hexagon: Implement modify SSR target/hexagon: Implement {g,s}etimask helpers target/hexagon: Implement wait helper target/hexagon: Implement get_exe_mode() target/hexagon: Implement arch_get_system_reg() target/hexagon: Implement arch_{s,g}et_{thread,system}_reg() target/hexagon: Add representation to count cycles target/hexagon: Add implementation of cycle counters target/hexagon: Implement modify_syscfg() target/hexagon: Add system event, cause codes target/hexagon: Implement hex_tlb_entry_get_perm() target/hexagon: Implement hex_tlb_lookup_by_asid() target/hexagon: Implement software interrupt target/hexagon: Implement exec_interrupt, set_irq target/hexagon: Implement hexagon_tlb_fill() target/hexagon: Implement siad inst target/hexagon: Implement hexagon_resume_threads() target/hexagon: Implement setprio, resched target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() target/hexagon: Add exec-start-addr prop target/hexagon: Add hexagon_cpu_mmu_index() target/hexagon: Decode trap1, rte as COF target/hexagon: Implement hexagon_find_last_irq() target/hexagon: Implement modify_ssr, resched, pending_interrupt target/hexagon: Add pkt_ends_tb to translation target/hexagon: Add next_PC, {s,g}reg writes target/hexagon: Add implicit sysreg writes target/hexagon: Define system, guest reg names target/hexagon: initialize sys/guest reg TCGvs target/hexagon: Add TLB, k0 {un,}lock target/hexagon: Define gen_precise_exception() target/hexagon: Add TCG overrides for transfer insts target/hexagon: Add support for loadw_phys target/hexagon: Add pcycle setting functionality Matheus Tavares Bernardino (1): target/hexagon: Add guest reg reading functionality target/hexagon/cpu.h | 51 +++- target/hexagon/cpu_bits.h | 56 +++- target/hexagon/cpu_helper.h | 19 +- target/hexagon/gen_tcg.h | 7 - target/hexagon/gen_tcg_sys.h | 25 ++ target/hexagon/helper.h | 5 +- target/hexagon/hexswi.h | 17 ++ target/hexagon/internal.h | 2 + target/hexagon/sys_macros.h | 8 +- target/hexagon/translate.h | 5 + target/hexagon/reg_fields_def.h.inc | 11 + target/hexagon/cpu.c | 336 +++++++++++++++++++- target/hexagon/cpu_helper.c | 374 ++++++++++++++++++++++- target/hexagon/decode.c | 14 + target/hexagon/genptr.c | 7 +- target/hexagon/hex_mmu.c | 80 ++++- target/hexagon/hexswi.c | 258 ++++++++++++++++ target/hexagon/machine.c | 25 +- target/hexagon/op_helper.c | 423 ++++++++++++++++++++++++-- target/hexagon/translate.c | 315 +++++++++++++++++-- target/hexagon/hex_common.py | 3 + target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/ldst.idef | 3 + 23 files changed, 1938 insertions(+), 107 deletions(-) create mode 100644 target/hexagon/hexswi.h create mode 100644 target/hexagon/hexswi.c