From patchwork Wed Aug 2 21:08:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 13338814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22A43C41513 for ; Wed, 2 Aug 2023 21:09:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qRJ4x-0003UO-Ur; Wed, 02 Aug 2023 17:08:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qRJ4v-0003Px-Rv; Wed, 02 Aug 2023 17:08:21 -0400 Received: from relay9-d.mail.gandi.net ([2001:4b98:dc4:8::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qRJ4t-0007ND-U6; Wed, 02 Aug 2023 17:08:21 -0400 Received: by mail.gandi.net (Postfix) with ESMTPSA id 04997FF805; Wed, 2 Aug 2023 21:08:11 +0000 (UTC) From: Jean-Christophe Dubois To: qemu-arm@nongnu.org Cc: Jean-Christophe Dubois , qemu-devel@nongnu.org Subject: [PATCH v3 0/5] Complete i.MX6UL and i.MX7 processor for bare metal application. Date: Wed, 2 Aug 2023 23:08:03 +0200 Message-Id: X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-GND-Sasl: jcd@tribudubois.net Received-SPF: pass client-ip=2001:4b98:dc4:8::229; envelope-from=jcd@tribudubois.net; helo=relay9-d.mail.gandi.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds a few unimplemented TZ devices (TZASC and CSU) to i.MX6UL and i.MX7 processors to avoid bare metal application to experiment "bus error" when acccessing these devices. It also adds some internal memory segments (OCRAM) to the i.MX7 to allow bare metal application to use them. Last, it adds the SRC device to the i.MX7 processor to allow bare metal application to start the secondary Cortex-A7 core. Note: When running Linux inside Qemu, the secondary core is started by calling PSCI API and Qemu is emulating PSCI without needing access to the SRC device. This is why Linux is using the 2 cores in Qemu even if the SRC is not implemented. This is not the case when running bare metal application (like u-boot itself) that do not rely on the PSCI service being available. Changes since v2: * use GiB, MiB, KiB constant defined in qemu/units.h after code review Changes since v1: * split the i.MX6UL patch into a refactor patch and an addon patch. * Split the i.MX7 patch into a refactor patch and an addon patch. * Fix SRC code after few comments in code review. Jean-Christophe Dubois (5): Refactor i.MX6UL processor code Add i.MX6UL TZ missing devices. Refactor i.MX7 processor code Add i.MX7 missing TZ devices and memory regions Add i.MX7 SRC device implementation hw/arm/fsl-imx6ul.c | 161 ++++++++++++----- hw/arm/fsl-imx7.c | 205 ++++++++++++++++----- hw/misc/imx7_src.c | 276 ++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 + include/hw/arm/fsl-imx6ul.h | 150 ++++++++++++++-- include/hw/arm/fsl-imx7.h | 349 +++++++++++++++++++++++++++--------- include/hw/misc/imx7_src.h | 66 +++++++ 8 files changed, 1028 insertions(+), 184 deletions(-) create mode 100644 hw/misc/imx7_src.c create mode 100644 include/hw/misc/imx7_src.h