From patchwork Tue Sep 10 12:18:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: lixianglai X-Patchwork-Id: 13798447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F9D2ECE564 for ; Tue, 10 Sep 2024 12:38:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1so07C-0004Jo-Tm; Tue, 10 Sep 2024 08:37:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1so06k-0002Gr-D7 for qemu-devel@nongnu.org; Tue, 10 Sep 2024 08:36:34 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1so06h-000539-FI for qemu-devel@nongnu.org; Tue, 10 Sep 2024 08:36:34 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxhehEPeBmYrkDAA--.7710S3; Tue, 10 Sep 2024 20:36:20 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front2 (Coremail) with SMTP id qciowMBx+cVCPeBmXGoDAA--.15753S2; Tue, 10 Sep 2024 20:36:19 +0800 (CST) From: Xianglai Li To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Song Gao , Jiaxun Yang , Huacai Chen , "Michael S. Tsirkin" , Cornelia Huck , kvm@vger.kernel.org, Bibo Mao Subject: [RFC PATCH V2 0/5] Added Interrupt controller emulation for loongarch kvm Date: Tue, 10 Sep 2024 20:18:27 +0800 Message-Id: X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-CM-TRANSID: qciowMBx+cVCPeBmXGoDAA--.15753S2 X-CM-SenderInfo: 5ol0xt5qjotxo6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=lixianglai@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Before this, the interrupt controller simulation has been completed in the user mode program. In order to reduce the loss caused by frequent switching of the virtual machine monitor from kernel mode to user mode when the guest accesses the interrupt controller, we add the interrupt controller simulation in kvm. In qemu side implementation is simple, just make a new IPI EXTIOI PCH KVM related several classes, And the interface to access kvm related data is implemented. Most of the simulation work of the interrupt controller is done in kvm. Because KVM the changes have not been the Linux community acceptance, the patches of this series will have RFC label until KVM patch into the community. For the implementation of kvm simulation, refer to the following documents. IPI simulation implementation reference: https://github.com/loongson/LoongArch-Documentation/tree/main/docs/Loongson-3A5000-usermanual-EN/inter-processor-interrupts-and-communication EXTIOI simulation implementation reference: https://github.com/loongson/LoongArch-Documentation/tree/main/docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts PCH-PIC simulation implementation reference: https://github.com/loongson/LoongArch-Documentation/blob/main/docs/Loongson-7A1000-usermanual-EN/interrupt-controller.adoc For PCH-MSI, we used irqfd mechanism to send the interrupt signal generated by user state to kernel state and then to EXTIOI without maintaining PCH-MSI state in kernel state. You can easily get the code from the link below: the kernel: https://github.com/lixianglai/linux the branch is: interrupt the qemu: https://github.com/lixianglai/qemu the branch is: interrupt Please note that the code above is regularly updated based on community reviews. changelog: V1->V2 1.Make changes involving header files a separate patch 2.rebase based on the latest qemu code 3.Optimize the kvm ipi class into the ipi common class and the ipi kvm class. 4.Optimized the interface for kernel reading and writing data on ipi extioi pch_pic device. Cc: Paolo Bonzini Cc: Song Gao Cc: Jiaxun Yang Cc: Huacai Chen Cc: "Michael S. Tsirkin" Cc: Cornelia Huck Cc: kvm@vger.kernel.org Cc: Bibo Mao Cc: Xianglai Li Xianglai Li (5): include: Add macro definitions needed for interrupt controller kvm emulation hw/loongarch: Add KVM IPI device support hw/loongarch: Add KVM extioi device support hw/loongarch: Add KVM pch pic device support hw/loongarch: Add KVM pch msi device support hw/intc/Kconfig | 9 + hw/intc/loongarch_extioi_kvm.c | 250 ++++++++++++++++++++++++++ hw/intc/loongarch_ipi_kvm.c | 128 +++++++++++++ hw/intc/loongarch_pch_msi.c | 42 +++-- hw/intc/loongarch_pch_pic.c | 40 +++-- hw/intc/loongarch_pch_pic_kvm.c | 180 +++++++++++++++++++ hw/intc/loongson_ipi_common.c | 28 +++ hw/intc/meson.build | 3 + hw/loongarch/Kconfig | 3 + hw/loongarch/virt.c | 138 ++++++++------ include/hw/intc/loongarch_extioi.h | 38 +++- include/hw/intc/loongarch_ipi.h | 15 ++ include/hw/intc/loongarch_pch_pic.h | 58 +++++- include/hw/intc/loongson_ipi.h | 1 - include/hw/intc/loongson_ipi_common.h | 2 + include/hw/loongarch/virt.h | 15 ++ linux-headers/asm-loongarch/kvm.h | 18 ++ linux-headers/linux/kvm.h | 6 + 18 files changed, 891 insertions(+), 83 deletions(-) create mode 100644 hw/intc/loongarch_extioi_kvm.c create mode 100644 hw/intc/loongarch_ipi_kvm.c create mode 100644 hw/intc/loongarch_pch_pic_kvm.c