Show patches with: Submitter = Max Chou       |    State = Action Required       |   152 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,05/15] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-02 Max Chou New
[v7,04/15] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-07-02 Max Chou New
[v7,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,02/15] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-07-02 Max Chou New
[v7,01/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v6,15/15] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,14/15] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,13/15] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v6,12/15] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,11/15] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,10/15] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,09/15] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,08/15] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,07/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,06/15] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v6,05/15] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v6,04/15] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-06-27 Max Chou New
[v6,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v6,02/15] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-06-27 Max Chou New
[v6,01/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,15/15] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,14/15] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,13/15] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v5,12/15] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,11/15] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,10/15] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,09/15] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,08/15] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,07/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,06/15] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v5,05/15] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-27 Max Chou New
[v5,04/15] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-06-27 Max Chou New
[v5,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v5,02/15] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-06-27 Max Chou New
[v5,01/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-27 Max Chou New
[v4,17/17] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,16/17] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,15/17] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,14/17] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-22 Max Chou New
[v4,13/17] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,12/17] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,11/17] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,10/17] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,09/17] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,07/17] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,06/17] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-22 Max Chou New
[v4,05/17] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-06-22 Max Chou New
[v4,04/17] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - --- 2023-06-22 Max Chou New
[v4,03/17] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
[v4,02/17] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-06-22 Max Chou New
[v4,01/17] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-06-22 Max Chou New
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