Show patches with: Submitter = LIU Zhiwei       |    State = Action Required       |   225 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
target/riscv: Fix page_check_range use in fault-only-first target/riscv: Fix page_check_range use in fault-only-first - 1 - --- 2023-07-29 LIU Zhiwei New
target/riscv: Fix zfa fleq.d and fltq.d target/riscv: Fix zfa fleq.d and fltq.d - 2 - --- 2023-07-28 LIU Zhiwei New
fpu: Add conversions between bfloat16 and [u]int8 fpu: Add conversions between bfloat16 and [u]int8 - - - --- 2023-05-31 LIU Zhiwei New
[1/1] target/riscv: Convert env->virt to a bool env->virt_enabled [1/1] target/riscv: Convert env->virt to a bool env->virt_enabled - 2 - --- 2023-03-25 LIU Zhiwei New
target/riscv: Fix itrigger when icount is used target/riscv: Fix itrigger when icount is used 1 1 - --- 2023-03-24 LIU Zhiwei New
[4/4] target/riscv: Add a tb flags field for vstart Fix tb flags use - 2 - --- 2023-03-24 LIU Zhiwei New
[3/4] target/riscv: Encode the FS and VS on a normal way for tb flags Fix tb flags use - 1 - --- 2023-03-24 LIU Zhiwei New
[2/4] target/riscv: Add a general status enum for extensions Fix tb flags use - - - --- 2023-03-24 LIU Zhiwei New
[1/4] target/riscv: Extract virt enabled state from tb flags Fix tb flags use - 2 - --- 2023-03-24 LIU Zhiwei New
tcg/tcg: Avoid TS_DEAD for basic block ending tcg/tcg: Avoid TS_DEAD for basic block ending - - - --- 2023-03-21 LIU Zhiwei New
target/riscv: Fix priv version dependency for vector and zfh target/riscv: Fix priv version dependency for vector and zfh - 2 - --- 2023-03-21 LIU Zhiwei New
target/riscv: Fix vslide1up.vf and vslide1down.vf target/riscv: Fix vslide1up.vf and vslide1down.vf - 2 - --- 2023-02-13 LIU Zhiwei New
[1/1] tcg/riscv: Fix base regsiter for qemu_ld/st [1/1] tcg/riscv: Fix base regsiter for qemu_ld/st - - - --- 2022-10-23 LIU Zhiwei New
[RFC,3/3] tcg/riscv: Remove a wrong optimization for addsub2 Fix some TCG RISC-V backend bugs - - - --- 2022-10-20 LIU Zhiwei New
[RFC,2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds Fix some TCG RISC-V backend bugs - - - --- 2022-10-20 LIU Zhiwei New
[RFC,1/3] tcg/riscv: Fix base regsiter for qemu_ld/st Fix some TCG RISC-V backend bugs - - - --- 2022-10-20 LIU Zhiwei New
[v1,4/4] target/riscv: Add itrigger_enabled field to CPURISCVState Support native debug icount trigger - 1 - --- 2022-10-13 LIU Zhiwei New
[v1,3/4] target/riscv: Enable native debug itrigger Support native debug icount trigger - 1 - --- 2022-10-13 LIU Zhiwei New
[v1,2/4] target/riscv: Add itrigger support when icount is enabled Support native debug icount trigger - 1 - --- 2022-10-13 LIU Zhiwei New
[v1,1/4] target/riscv: Add itrigger support when icount is not enabled Support native debug icount trigger - 1 - --- 2022-10-13 LIU Zhiwei New
target/riscv: Fix PMP propagation for tlb target/riscv: Fix PMP propagation for tlb - 1 - --- 2022-10-12 LIU Zhiwei New
[RFC,4/4] target/riscv: Support Ventana disassemble Support multiple deocde path for RISC-V - - - --- 2022-08-24 LIU Zhiwei New
[RFC,3/4] disas/riscv: Add used_opcode_data field Support multiple deocde path for RISC-V - - - --- 2022-08-24 LIU Zhiwei New
[RFC,2/4] disas/riscv: Move down the struct rv_decode Support multiple deocde path for RISC-V - - - --- 2022-08-24 LIU Zhiwei New
[RFC,1/4] target/riscv: Use xl instead of mxl for disassemble Support multiple deocde path for RISC-V - 2 - --- 2022-08-24 LIU Zhiwei New
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