Show patches with: Submitter = Palmer Dabbelt       |    State = Action Required       |   724 patches
« 1 2 ... 3 4 5 … 7 8 »
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,11/47] riscv: Resolve full path of the given bios image [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,10/47] riscv: Add a helper routine for finding firmware [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,09/47] riscv: rv32: Root page table address can be larger than 32-bit [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,08/47] target/riscv: Update the Hypervisor CSRs to v0.4 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,07/47] target/riscv: Create function to test if FP is enabled [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 2 - --- 2019-09-10 Palmer Dabbelt New
[PULL,06/47] riscv: plic: Remove unused interrupt functions [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 3 - --- 2019-09-10 Palmer Dabbelt New
[PULL,05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,03/47] riscv: sifive_u: Fix clock-names property for ethernet node [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL,01/47] riscv: sifive_u: Add support for loading initrd [PULL,01/47] riscv: sifive_u: Add support for loading initrd - 1 - --- 2019-09-10 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1 - - - --- 2019-09-10 Palmer Dabbelt New
[v2] RISC-V: Ignore the S and U letters when formatting ISA strings [v2] RISC-V: Ignore the S and U letters when formatting ISA strings - 1 - --- 2019-08-13 Palmer Dabbelt New
[v2] RISC-V: Ignore the S and U extensions when formatting ISA strings [v2] RISC-V: Ignore the S and U extensions when formatting ISA strings - - - --- 2019-08-07 Palmer Dabbelt New
[for,4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings [for,4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings - - - --- 2019-08-07 Palmer Dabbelt New
[PULL] riscv/boot: Fixup the RISC-V firmware warning [PULL] riscv/boot: Fixup the RISC-V firmware warning - 1 - --- 2019-07-26 Palmer Dabbelt New
[PULL] RISC-V Patch for 4.1-rc3 [PULL] RISC-V Patch for 4.1-rc3 - - - --- 2019-07-26 Palmer Dabbelt New
[PULL,2/2] hw/riscv: Load OpenSBI as the default firmware [PULL] RISC-V Patches for 4.2-rc2 - 2 2 --- 2019-07-19 Palmer Dabbelt New
[PULL,1/2] roms: Add OpenSBI version 0.4 [PULL,1/2] roms: Add OpenSBI version 0.4 - 2 1 --- 2019-07-19 Palmer Dabbelt New
[PULL] RISC-V Patches for 4.2-rc2 [PULL] RISC-V Patches for 4.2-rc2 - - - --- 2019-07-19 Palmer Dabbelt New
[PULL,32/32] hw/riscv: Extend the kernel loading support [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 1 --- 2019-07-03 Palmer Dabbelt New
[PULL,31/32] hw/riscv: Add support for loading a firmware [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 1 --- 2019-07-03 Palmer Dabbelt New
[PULL,30/32] hw/riscv: Split out the boot functions [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 1 --- 2019-07-03 Palmer Dabbelt New
[PULL,29/32] riscv: sifive_u: Update the plic hart config to support multicore [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,28/32] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,27/32] disas/riscv: Fix `rdinstreth` constraint [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,26/32] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,25/32] riscv: virt: Add cpu-topology DT node. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,24/32] RISC-V: Update syscall list for 32-bit support. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,23/32] RISC-V: Clear load reservations on context switch and SC [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 2 - --- 2019-07-03 Palmer Dabbelt New
[PULL,22/32] RISC-V: Add support for the Zicsr extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,21/32] RISC-V: Add support for the Zifencei extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,20/32] target/riscv: Add support for disabling/enabling Counters [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,19/32] target/riscv: Remove user version information [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,18/32] target/riscv: Require either I or E base extension [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - - --- 2019-07-03 Palmer Dabbelt New
[PULL,16/32] target/riscv: Set privledge spec 1.11.0 as default [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,15/32] target/riscv: Add the mcountinhibit CSR [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,14/32] target/riscv: Add the privledge spec version 1.11.0 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,13/32] target/riscv: Restructure deprecatd CPUs [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,12/32] RISC-V: Fix a memory leak when realizing a sifive_e [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 2 - --- 2019-07-03 Palmer Dabbelt New
[PULL,11/32] riscv: virt: Correct pci "bus-range" encoding [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,10/32] RISC-V: Fix a PMP check with the correct access size [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,08/32] RISC-V: Check PMP during Page Table Walks [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,07/32] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,06/32] RISC-V: Raise access fault exceptions on PMP violations [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,05/32] RISC-V: Only Check PMP if MMU translation succeeds [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,04/32] target/riscv: Implement riscv_cpu_unassigned_access [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,03/32] target/riscv: Fix PMP range boundary address bug [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 2 - --- 2019-07-03 Palmer Dabbelt New
[PULL,02/32] sifive_prci: Read and write PRCI registers [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - 1 - --- 2019-07-03 Palmer Dabbelt New
[PULL,01/32] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/32] target/riscv: Allow setting ISA extensions via CPU props - - - --- 2019-07-03 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 - - - --- 2019-07-03 Palmer Dabbelt New
[PULL,34/34] hw/riscv: Load OpenSBI as the default firmware [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,33/34] roms: Add OpenSBI version 0.3 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,32/34] hw/riscv: Extend the kernel loading support [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,31/34] hw/riscv: Add support for loading a firmware [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,30/34] hw/riscv: Split out the boot functions [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 1 --- 2019-06-28 Palmer Dabbelt New
[PULL,29/34] riscv: sifive_u: Update the plic hart config to support multicore [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,28/34] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,27/34] disas/riscv: Fix `rdinstreth` constraint [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,26/34] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,25/34] riscv: virt: Add cpu-topology DT node. [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,24/34] RISC-V: Update syscall list for 32-bit support. [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,23/34] RISC-V: Clear load reservations on context switch and SC [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,22/34] RISC-V: Add support for the Zicsr extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,21/34] RISC-V: Add support for the Zifencei extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,20/34] target/riscv: Add support for disabling/enabling Counters [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,19/34] target/riscv: Remove user version information [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,18/34] target/riscv: Require either I or E base extension [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - --- 2019-06-28 Palmer Dabbelt New
[PULL,16/34] target/riscv: Set privledge spec 1.11.0 as default [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,15/34] target/riscv: Add the mcountinhibit CSR [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,14/34] target/riscv: Add the privledge spec version 1.11.0 [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,13/34] target/riscv: Restructure deprecatd CPUs [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,12/34] RISC-V: Fix a memory leak when realizing a sifive_e [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,11/34] riscv: virt: Correct pci "bus-range" encoding [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,10/34] RISC-V: Fix a PMP check with the correct access size [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,08/34] RISC-V: Check PMP during Page Table Walks [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,07/34] RISC-V: Check for the effective memory privilege mode during PMP checks [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,06/34] RISC-V: Raise access fault exceptions on PMP violations [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,05/34] RISC-V: Only Check PMP if MMU translation succeeds [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,04/34] target/riscv: Implement riscv_cpu_unassigned_access [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,03/34] target/riscv: Fix PMP range boundary address bug [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 2 - --- 2019-06-28 Palmer Dabbelt New
[PULL,02/34] sifive_prci: Read and write PRCI registers [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - 1 - --- 2019-06-28 Palmer Dabbelt New
[PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props [PULL,01/34] target/riscv: Allow setting ISA extensions via CPU props - - - --- 2019-06-28 Palmer Dabbelt New
[PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 - - - --- 2019-06-28 Palmer Dabbelt New
[PULL,34/34] hw/riscv: Load OpenSBI as the default firmware [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 1 --- 2019-06-27 Palmer Dabbelt New
[PULL,33/34] roms: Add OpenSBI version 0.3 [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 1 --- 2019-06-27 Palmer Dabbelt New
[PULL,32/34] hw/riscv: Extend the kernel loading support [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 1 --- 2019-06-27 Palmer Dabbelt New
[PULL,31/34] hw/riscv: Add support for loading a firmware [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 1 --- 2019-06-27 Palmer Dabbelt New
[PULL,30/34] hw/riscv: Split out the boot functions [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 1 --- 2019-06-27 Palmer Dabbelt New
[PULL,29/34] riscv: sifive_u: Update the plic hart config to support multicore [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,28/34] riscv: sifive_u: Do not create hard-coded phandles in DT [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,27/34] disas/riscv: Fix `rdinstreth` constraint [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,26/34] disas/riscv: Disassemble reserved compressed encodings as illegal [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,25/34] riscv: virt: Add cpu-topology DT node. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,24/34] RISC-V: Update syscall list for 32-bit support. [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 1 - --- 2019-06-27 Palmer Dabbelt New
[PULL,23/34] RISC-V: Clear load reservations on context switch and SC [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 - 2 - --- 2019-06-27 Palmer Dabbelt New
« 1 2 ... 3 4 5 … 7 8 »