Show patches with: Series = [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode       |    State = Action Required       |   18 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,18/18] target/riscv: PMP violation due to wrong size parameter [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,17/18] riscv/boot: Fix possible memory leak [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 3 - --- 2019-10-28 Palmer Dabbelt New
[PULL,16/18] target/riscv: Make the priv register writable by GDB [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,15/18] target/riscv: Expose "priv" register for GDB for reads [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,14/18] target/riscv: Tell gdbstub the correct number of CSRs [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,13/18] riscv/virt: Jump to pflash if specified [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,12/18] riscv/virt: Add the PFlash CFI01 device [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,11/18] riscv/virt: Manually define the machine [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,10/18] riscv/sifive_u: Add the start-in-flash property [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,09/18] riscv/sifive_u: Manually define the machine [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 1 --- 2019-10-28 Palmer Dabbelt New
[PULL,08/18] riscv/sifive_u: Add QSPI memory region [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,07/18] riscv/sifive_u: Add L2-LIM cache memory [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,06/18] linux-user/riscv: Propagate fault address [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,05/18] riscv: sifive_u: Add ethernet0 to the aliases node [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New
[PULL,03/18] RISC-V: Implement cpu_do_transaction_failed [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,02/18] RISC-V: Handle bus errors in the page table walker [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 2 - --- 2019-10-28 Palmer Dabbelt New
[PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode [PULL,01/18] riscv: Skip checking CSR privilege level in debugger mode - 1 - --- 2019-10-28 Palmer Dabbelt New