Show patches with: Series = [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong       |    State = Action Required       |   38 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,37/38] target/riscv: Emulate TIME CSRs for privileged mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,36/38] riscv: virt: Allow PCI address 0 [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,35/38] target/riscv: Allow enabling the Hypervisor extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,32/38] target/riscv: Set htval and mtval2 on execptions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,31/38] target/riscv: Raise the new execptions when 2nd stage translation fails [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,30/38] target/riscv: Implement second stage MMU [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,29/38] target/riscv: Allow specifying MMU stage [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,28/38] target/riscv: Respect MPRV and SPRV for floating point ops [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,26/38] target/riscv: Disable guest FP support based on virtual status [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,25/38] target/riscv: Only set TB flags with FP status if enabled [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,24/38] target/riscv: Remove the hret instruction [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,23/38] target/riscv: Add hfence instructions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,22/38] target/riscv: Add Hypervisor trap return support [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,21/38] target/riscv: Add hypvervisor trap support [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,20/38] target/riscv: Generate illegal instruction on WFI when V=1 [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,19/38] target/ricsv: Flush the TLB on virtulisation mode changes [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,18/38] target/riscv: Add support for virtual interrupt setting [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,17/38] target/riscv: Extend the SIP CSR to support virtulisation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,16/38] target/riscv: Extend the MIE CSR to support virtulisation [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,15/38] target/riscv: Set VS bits in mideleg for Hyp extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,14/38] target/riscv: Add virtual register swapping function [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,13/38] target/riscv: Add Hypervisor machine CSRs accesses [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,12/38] target/riscv: Add Hypervisor virtual CSRs accesses [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,11/38] target/riscv: Add Hypervisor CSR access functions [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,10/38] target/riscv: Dump Hypervisor registers if enabled [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,09/38] target/riscv: Print priv and virt in disas log [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,08/38] target/riscv: Fix CSR perm checking for HS mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,07/38] target/riscv: Add the force HS exception mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,06/38] target/riscv: Add the virtulisation mode [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,05/38] target/riscv: Rename the H irqs to VS irqs [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,04/38] target/riscv: Add support for the new execption numbers [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,03/38] target/riscv: Add the Hypervisor CSRs to CPUState [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New
[PULL,02/38] target/riscv: Add the Hypervisor extension [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 2 - --- 2020-03-03 Palmer Dabbelt New
[PULL,01/38] target/riscv: Convert MIP CSR to target_ulong [PULL,01/38] target/riscv: Convert MIP CSR to target_ulong - 1 - --- 2020-03-03 Palmer Dabbelt New