Show patches with: Series = [PULL] RISC-V Changes for 3.2, Part 1       |   14 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,13/14] riscv/cpu: use device_class_set_parent_realize [PULL] RISC-V Changes for 3.2, Part 1 - 2 - --- 2018-12-26 Palmer Dabbelt New
[PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,11/14] sifive_uart: Implement interrupt pending register [PULL] RISC-V Changes for 3.2, Part 1 - 2 - --- 2018-12-26 Palmer Dabbelt New
[PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,09/14] RISC-V: Fix PLIC pending bitfield reads [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,07/14] RISC-V: Add hartid and \n to interrupt logging [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet [PULL] RISC-V Changes for 3.2, Part 1 - 1 - --- 2018-12-26 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA [PULL] RISC-V Changes for 3.2, Part 1 - 1 1 --- 2018-12-26 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe [PULL] RISC-V Changes for 3.2, Part 1 - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing [PULL] RISC-V Changes for 3.2, Part 1 - 1 2 --- 2018-12-26 Palmer Dabbelt New
[PULL] RISC-V Changes for 3.2, Part 1 [PULL] RISC-V Changes for 3.2, Part 1 - - - --- 2018-12-26 Palmer Dabbelt New