Show patches with: Series = [PULL,01/59] target/riscv: introduce riscv_cpu_cfg()       |    State = Action Required       |   59 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PULL,59/59] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,58/59] target/riscv/vector_helper.c: create vext_set_tail_elems_1s() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,57/59] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,56/59] target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,55/59] target/riscv/csr.c: simplify mctr() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,54/59] target/riscv/csr.c: use env_archcpu() in ctr() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,53/59] target/riscv: Export Svadu property [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,52/59] target/riscv: Add *envcfg.HADE related check in address translation [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,51/59] target/riscv: Add *envcfg.PBMTE related check in address translation [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,50/59] target/riscv: Add csr support for svadu [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensio… [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,47/59] hw/riscv: Move the dtb load bits outside of create_fdt() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,46/59] hw/riscv: Skip re-generating DT nodes for a given DTB [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,45/59] target/riscv: Add support for Zicond extension [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,42/59] target/riscv: Group all predicate() routines together [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,41/59] target/riscv: Drop priv level check in mseccfg predicate() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,40/59] target/riscv: Allow debugger to access sstc CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,38/59] target/riscv: Allow debugger to access seed CSR [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,37/59] target/riscv: Allow debugger to access user timer and counter CSRs [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,33/59] target/riscv: Simplify getting RISCVCPU pointer from env [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,31/59] target/riscv: Use 'bool' type for read_only [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,30/59] target/riscv: Coding style fixes in csr.c [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,28/59] target/riscv: gdbstub: Minor change for better readability [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,27/59] target/riscv: Use g_assert() for the predicate() NULL check [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 2 - --- 2023-03-03 Palmer Dabbelt New
[PULL,24/59] target/riscv: Expose properties for Zv* extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,22/59] target/riscv: Fix check for vector load/store instructions when EEW=64 [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,21/59] target/riscv: Add support for Zvfh/zvfhmin extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,20/59] target/riscv: Remove redundunt check for zve32f and zve64f [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,18/59] target/riscv: Simplify check for Zve32f and Zve64f [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,17/59] target/riscv: Indent fixes in cpu.c [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,16/59] target/riscv: Add property check for Zvfh{min} extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,15/59] target/riscv: Fix relationship between V, Zve*, F and D [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,14/59] target/riscv: Add cfg properties for Zv* extensions [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,11/59] target/riscv: Fix the relationship between Zfhmin and Zfh [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 1 - --- 2023-03-03 Palmer Dabbelt New
[PULL,10/59] target/riscv/cpu: remove CPUArchState::features and friends [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,09/59] target/riscv: remove RISCV_FEATURE_MMU [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,07/59] target/riscv: remove RISCV_FEATURE_PMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,06/59] target/riscv: remove RISCV_FEATURE_EPMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,04/59] target/riscv: remove RISCV_FEATURE_DEBUG [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New
[PULL,03/59] target/riscv: allow MISA writes as experimental [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 5 - --- 2023-03-03 Palmer Dabbelt New
[PULL,02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 3 - --- 2023-03-03 Palmer Dabbelt New
[PULL,01/59] target/riscv: introduce riscv_cpu_cfg() [PULL,01/59] target/riscv: introduce riscv_cpu_cfg() - 4 - --- 2023-03-03 Palmer Dabbelt New