Show patches with: Series = Add RISC-V Counter delegation ISA extension support       |    State = Action Required       |   11 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v5,11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,10/11] target/riscv: Add implied rule for counter delegation extensions Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,09/11] target/riscv: Invoke pmu init after feature enable Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,08/11] target/riscv: Add counter delegation/configuration support Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,07/11] target/riscv: Add select value range check for counter delegation Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,06/11] target/riscv: Add counter delegation definitions Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,05/11] target/riscv: Add properties for counter delegation ISA extensions Add RISC-V Counter delegation ISA extension support - 2 - --- 2025-01-10 Atish Kumar Patra New
[v5,04/11] target/riscv: Support generic CSR indirect access Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,03/11] target/riscv: Enable S*stateen bits for AIA Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,02/11] target/riscv: Decouple AIA processing from xiselect and xireg Add RISC-V Counter delegation ISA extension support - 1 - --- 2025-01-10 Atish Kumar Patra New
[v5,01/11] target/riscv: Add properties for Indirect CSR Access extension Add RISC-V Counter delegation ISA extension support 1 1 - --- 2025-01-10 Atish Kumar Patra New