Show patches with: Submitter = Max Chou       |   152 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,7/7] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 2 - --- 2024-09-18 Max Chou New
[v6,6/7] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,5/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride loa… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,4/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride who… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,3/7] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-s… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,2/7] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[v6,1/7] target/riscv: Set vdata.vm field for vector load/store whole register instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-09-18 Max Chou New
[RFC,v5,5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-07-17 Max Chou New
[RFC,v5,4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructi… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-07-17 Max Chou New
[RFC,v5,3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-07-17 Max Chou New
[RFC,v5,2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked un… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-07-17 Max Chou New
[RFC,v5,1/5] target/riscv: Set vdata.vm field for vector load/store whole register instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-07-17 Max Chou New
[RFC,v4,5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-06-13 Max Chou New
[RFC,v4,4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructi… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v4,3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v4,2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked un… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v4,1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 2 - --- 2024-06-13 Max Chou New
[RFC,v3,5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v3,4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructi… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v3,3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v3,2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked un… Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v3,1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-06-13 Max Chou New
[RFC,v2,6/6] target/riscv: rvv: Optimize vl8re8.v/vs8r.v with limitations Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-05-31 Max Chou New
[RFC,v2,5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-05-31 Max Chou New
[RFC,v2,4/6] target/riscv: Add check_probe_[read|write] helper functions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-05-31 Max Chou New
[RFC,v2,3/6] target/riscv: Inline vext_ldst_us and corresponding function for performance Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - 1 - --- 2024-05-31 Max Chou New
[RFC,v2,2/6] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-05-31 Max Chou New
[RFC,v2,1/6] target/riscv: Separate vector segment ld/st instructions Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions - - - --- 2024-05-31 Max Chou New
[v2,4/4] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Fix fp16 checking in vector fp widen/narrow instructions - 1 - --- 2024-03-22 Max Chou New
[v2,3/4] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Fix fp16 checking in vector fp widen/narrow instructions - 1 - --- 2024-03-22 Max Chou New
[v2,2/4] target/riscv: rvv: Check single width operator for vector fp widen instructions Fix fp16 checking in vector fp widen/narrow instructions - 1 - --- 2024-03-22 Max Chou New
[v2,1/4] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Fix fp16 checking in vector fp widen/narrow instructions - 1 - --- 2024-03-22 Max Chou New
target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin - 1 - --- 2024-03-21 Max Chou New
target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions - 1 - --- 2024-03-20 Max Chou New
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w - 1 - --- 2024-03-20 Max Chou New
target/riscv: rvv: Check single width operator for vector fp widen instructions target/riscv: rvv: Check single width operator for vector fp widen instructions - 1 - --- 2024-03-20 Max Chou New
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions - 1 - --- 2024-03-20 Max Chou New
target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking target/riscv/vector_helper.c: Avoid shifting negative in fractional LMUL checking - - - --- 2024-03-06 Max Chou New
[RFC,6/6] accel/tcg: Inline do_st1_mmu function Improve the performance of RISC-V vector unit-stride ld/st instructions - - - --- 2024-02-15 Max Chou New
[RFC,5/6] accel/tcg: Inline do_ld1_mmu function Improve the performance of RISC-V vector unit-stride ld/st instructions - - - --- 2024-02-15 Max Chou New
[RFC,4/6] accel/tcg: Inline cpu_mmu_lookup function Improve the performance of RISC-V vector unit-stride ld/st instructions - - - --- 2024-02-15 Max Chou New
[RFC,3/6] target/riscv: Inline vext_ldst_us and coressponding function for performance Improve the performance of RISC-V vector unit-stride ld/st instructions - 1 - --- 2024-02-15 Max Chou New
[RFC,2/6] accel/tcg: Avoid uncessary call overhead from qemu_plugin_vcpu_mem_cb Improve the performance of RISC-V vector unit-stride ld/st instructions - - - --- 2024-02-15 Max Chou New
[RFC,1/6] target/riscv: Seperate vector segment ld/st instructions Improve the performance of RISC-V vector unit-stride ld/st instructions - - - --- 2024-02-15 Max Chou New
[2/2] target/riscv: The whole vector register move instructions depend on vsew Make vector whole-register move (vmv) depend on vtype register 1 - - --- 2023-11-29 Max Chou New
[1/2] target/riscv: Add vill check for whole vector register move instructions Make vector whole-register move (vmv) depend on vtype register - 1 - --- 2023-11-29 Max Chou New
[v2,14/14] disas/riscv: Replace TABs with space Update RISC-V vector crypto to ratified v1.0.0 1 - - --- 2023-10-26 Max Chou New
[v2,13/14] disas/riscv: Add support for vector crypto extensions Update RISC-V vector crypto to ratified v1.0.0 1 - - --- 2023-10-26 Max Chou New
[v2,12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Update RISC-V vector crypto to ratified v1.0.0 1 - - --- 2023-10-26 Max Chou New
[v2,11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Update RISC-V vector crypto to ratified v1.0.0 1 - - --- 2023-10-26 Max Chou New
[v2,10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,09/14] target/riscv: Expose Zvks[c|g] extnesion properties Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,05/14] target/riscv: Expose Zvkb extension property Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,04/14] target/riscv: Replace Zvbb checking by Zvkb Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,03/14] target/riscv: Add cfg property for Zvkb extension Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,02/14] target/riscv: Expose Zvkt extension property Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[v2,01/14] target/riscv: Add cfg property for Zvkt extension Update RISC-V vector crypto to ratified v1.0.0 1 1 - --- 2023-10-26 Max Chou New
[14/14] disas/riscv: Replace TABs with space Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[13/14] disas/riscv: Add support for vector crypto extensions Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[09/14] target/riscv: Expose Zvks[c|g] extnesion properties Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[05/14] target/riscv: Expose Zvkb extension property Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[04/14] target/riscv: Replace Zvbb checking by Zvkb Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[03/14] target/riscv: Add cfg property for Zvkb extension Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[02/14] target/riscv: Expose Zvkt extension property Update RISC-V vector crypto to ratified v1.0.0 - - - --- 2023-10-25 Max Chou New
[01/14] target/riscv: Add cfg property for Zvkt extension Update RISC-V vector crypto to ratified v1.0.0 - 1 - --- 2023-10-25 Max Chou New
target/riscv: Fix vfwmaccbf16.vf target/riscv: Fix vfwmaccbf16.vf - 2 - --- 2023-10-05 Max Chou New
[v8,15/15] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,14/15] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-11 Max Chou New
[v8,13/15] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-11 Max Chou New
[v8,12/15] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,11/15] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,10/15] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,09/15] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,08/15] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support 1 1 - --- 2023-07-11 Max Chou New
[v8,07/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-11 Max Chou New
[v8,06/15] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-11 Max Chou New
[v8,05/15] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-11 Max Chou New
[v8,04/15] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support 1 - - --- 2023-07-11 Max Chou New
[v8,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support 1 1 - --- 2023-07-11 Max Chou New
[v8,02/15] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - 3 - --- 2023-07-11 Max Chou New
[v8,01/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support 1 1 - --- 2023-07-11 Max Chou New
[v7,15/15] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,14/15] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,13/15] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-02 Max Chou New
[v7,12/15] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,11/15] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,10/15] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,09/15] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,08/15] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,07/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - 1 - --- 2023-07-02 Max Chou New
[v7,06/15] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - 2 - --- 2023-07-02 Max Chou New
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