Show patches with: Submitter = Paolo Savini       |   10 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[RFC,v5,1/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and … target/riscv: rvv: reduce the overhead for simple RISC-V vector. - 1 - --- 2024-11-11 Paolo Savini New
[RFC,v4,2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amou… target/riscv: add wrapper for target specific macros in atomicity check. - - - --- 2024-10-29 Paolo Savini New
[RFC,v4,1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and … target/riscv: add wrapper for target specific macros in atomicity check. - 1 - --- 2024-10-29 Paolo Savini New
[RFC,v3,2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amou… target/riscv: add endianness checks and atomicity guarantees. - - - --- 2024-10-14 Paolo Savini New
[RFC,v3,1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and … target/riscv: add endianness checks and atomicity guarantees. - - - --- 2024-10-14 Paolo Savini New
[RFC,v2,2/2] target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. - - - --- 2024-10-02 Paolo Savini New
[RFC,v2,1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and … target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. - - - --- 2024-10-02 Paolo Savini New
[RFC,1/1] target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. target/riscv: use a simplified loop to emulate rvv loads/stores only in user mode. - - - --- 2024-09-25 Paolo Savini New
[RFC,2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts… Improve the performance of unit-stride RVV ld/st on - - - --- 2024-07-17 Paolo Savini New
[RFC,1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and sto… Improve the performance of unit-stride RVV ld/st on - - - --- 2024-07-17 Paolo Savini New