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LIU Zhiwei
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«
1
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
[v1,7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU
target/riscv: Support SXL32 on RV64 CPU
- - -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,6/7] target/riscv: Reset SXL and UXL according to sxl32
target/riscv: Support SXL32 on RV64 CPU
- - -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32
target/riscv: Support SXL32 on RV64 CPU
- - -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,4/7] hw/riscv: Align kernel to 4MB when sxl32 is on.
target/riscv: Support SXL32 on RV64 CPU
- - -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,3/7] target/riscv: Read pte and satp based on SXL in PTW
target/riscv: Support SXL32 on RV64 CPU
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,2/7] target/riscv: Fix satp read and write implicitly or explicitly.
target/riscv: Support SXL32 on RV64 CPU
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v1,1/7] target/riscv: Fix sstatus read and write
target/riscv: Support SXL32 on RV64 CPU
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,12/12] tcg/riscv: Enable native vector support for TCG host
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,11/12] tcg/riscv: Implement vector roti/v/x ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,10/12] tcg/riscv: Implement vector shi/s/v ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,09/12] tcg/riscv: Implement vector min/max ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,08/12] tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,07/12] tcg/riscv: Implement vector neg ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,06/12] tcg/riscv: Implement vector cmp/cmpsel ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,05/12] tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,04/12] tcg/riscv: Implement vector mov/dup{m/i}
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,02/12] tcg/riscv: Add basic support for vector
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v5,01/12] util: Add RISC-V vector extension probe in cpuinfo
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-10-07
LIU Zhiwei
New
[v7,8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
1 1 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,7/8] target/riscv: Add max32 CPU for RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v7,1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
-
-
-
2024-09-19
LIU Zhiwei
New
[v4,12/12] tcg/riscv: Enable native vector support for TCG host
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,11/12] tcg/riscv: Implement vector roti/v/x ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,10/12] tcg/riscv: Implement vector shi/s/v ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,09/12] tcg/riscv: Implement vector min/max ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,08/12] tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,07/12] tcg/riscv: Implement vector neg ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,06/12] tcg/riscv: Implement vector cmp/cmpsel ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,05/12] tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,04/12] tcg/riscv: Implement vector mov/dup{m/i}
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,02/12] tcg/riscv: Add basic support for vector
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v4,01/12] util: Add RISC-V vector extension probe in cpuinfo
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-09-11
LIU Zhiwei
New
[v3,14/14] tcg/riscv: Enable native vector support for TCG host
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,13/14] tcg/riscv: Implement vector roti/v/x shi ops
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,12/14] tcg/riscv: Implement vector shs/v ops
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,11/14] tcg/riscv: Implement vector min/max ops
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,10/14] tcg/riscv: Implement vector sat/mul ops
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,09/14] tcg/riscv: Implement vector neg ops
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,08/14] tcg/riscv: Implement vector cmp ops
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,07/14] tcg/riscv: Add support for basic vector opcodes
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,06/14] tcg/riscv: Implement vector mov/dup{m/i}
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,05/14] tcg/riscv: Implement vector load/store
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,04/14] tcg/riscv: Add riscv vset{i}vli support
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,03/14] tcg/riscv: Add basic support for vector
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,02/14] util: Add RISC-V vector extension probe in cpuinfo
Add support for vector
- 1 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v3,01/14] tcg/op-gvec: Fix iteration step in 32-bit operation
Add support for vector
- 2 -
-
-
-
2024-09-04
LIU Zhiwei
New
[v2,14/14] tcg/riscv: Enable native vector support for TCG host
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,13/14] tcg/riscv: Implement vector roti/v/x shi ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,12/14] tcg/riscv: Implement vector shs/v ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,11/14] tcg/riscv: Implement vector min/max ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,10/14] tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,09/14] tcg/riscv: Implement vector neg ops
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,08/14] tcg/riscv: Implement vector cmp ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,07/14] tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,06/14] tcg/riscv: Implement vector mov/dup{m/i}
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,05/14] tcg/riscv: Implement vector load/store
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,04/14] tcg/riscv: Add riscv vset{i}vli support
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,03/14] tcg/riscv: Add basic support for vector
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,02/14] util: Add RISC-V vector extension probe in cpuinfo
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v2,01/14] tcg/op-gvec: Fix iteration step in 32-bit operation
tcg/riscv: Add support for vector
- 2 -
-
-
-
2024-08-30
LIU Zhiwei
New
[v1,15/15] tcg/riscv: Enable vector TCG host-native
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,14/15] tcg/riscv: Implement vector roti/v/x shi ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,13/15] tcg/riscv: Implement vector shs/v ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,12/15] tcg/riscv: Implement vector min/max ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,11/15] tcg/riscv: Implement vector sat/mul ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,10/15] tcg/riscv: Implement vector not/neg ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,09/15] tcg/riscv: Implement vector cmp ops
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,08/15] tcg/riscv: Add support for basic vector opcodes
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,07/15] tcg/riscv: Implement vector mov/dup{m/i}
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,06/15] tcg/riscv: Implement vector load/store
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,05/15] tcg/riscv: Add riscv vset{i}vli support
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,04/15] tcg/riscv: Add basic support for vector
tcg/riscv: Add support for vector
- 1 -
-
-
-
2024-08-13
LIU Zhiwei
New
[v1,03/15] tcg: Fix register allocation constraints
tcg/riscv: Add support for vector
- 1 -
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2024-08-13
LIU Zhiwei
New
[v1,02/15] tcg/op-gvec: Fix iteration step in 32-bit operation
tcg/riscv: Add support for vector
- 1 -
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2024-08-13
LIU Zhiwei
New
[v1,01/15] util: Add RISC-V vector extension probe in cpuinfo
tcg/riscv: Add support for vector
- 1 -
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2024-08-13
LIU Zhiwei
New
[v3,3/3] target/riscv: Relax fld alignment requirement
target/riscv: Remove redundant insn length check for zama16b
- 2 -
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2024-08-02
LIU Zhiwei
New
[v3,2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b
target/riscv: Remove redundant insn length check for zama16b
- 2 -
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2024-08-02
LIU Zhiwei
New
[v3,1/3] target/riscv: Remove redundant insn length check for zama16b
target/riscv: Remove redundant insn length check for zama16b
- 2 -
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2024-08-02
LIU Zhiwei
New
[v2,3/3] target/riscv: Relax fld alignment requirement
target/riscv: Remove redundant insn length check for zama16b
- - -
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2024-08-02
LIU Zhiwei
New
[v2,2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b
target/riscv: Remove redundant insn length check for zama16b
- - -
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2024-08-02
LIU Zhiwei
New
[v2,1/3] target/riscv: Remove redundant insn length check for zama16b
target/riscv: Remove redundant insn length check for zama16b
- - -
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2024-08-02
LIU Zhiwei
New
[1/1] target/riscv: Remove redundant insn length check for zama16b
[1/1] target/riscv: Remove redundant insn length check for zama16b
- - -
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2024-07-23
LIU Zhiwei
New
[v6,8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
1 1 -
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2024-07-19
LIU Zhiwei
New
[v6,7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 1 -
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2024-07-19
LIU Zhiwei
New
[v6,6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v6,5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v6,4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v6,3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v6,2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v6,1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-19
LIU Zhiwei
New
[v5,7/7] tests/avocado: Add an avocado test for riscv64
target/riscv: Expose RV32 cpu to RV64 QEMU
1 1 -
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2024-07-10
LIU Zhiwei
New
[v5,6/7] target/riscv: Enable RV32 CPU support in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-10
LIU Zhiwei
New
[v5,5/7] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Expose RV32 cpu to RV64 QEMU
- 2 -
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2024-07-10
LIU Zhiwei
New
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