Show patches with: Submitter = Jason Chien       |    State = Action Required       |   28 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2] hw/riscv/riscv-iommu.c: Correct the validness check of iova [v2] hw/riscv/riscv-iommu.c: Correct the validness check of iova - 1 - --- 2024-11-14 Jason Chien New
hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache - - - --- 2024-11-08 Jason Chien New
[1/1] hw/riscv/riscv-iommu.c: Correct the validness check of iova [1/1] hw/riscv/riscv-iommu.c: Correct the validness check of iova - 1 - --- 2024-11-08 Jason Chien New
target/riscv: Add a property to set vl to ceil(AVL/2) target/riscv: Add a property to set vl to ceil(AVL/2) - 1 - --- 2024-07-22 Jason Chien New
[v3,3/3] target/riscv: Relax vector register check in RISCV gdbstub target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-28 Jason Chien New
[v3,2/3] target/riscv: Add support for Zve64x extension target/riscv: Support Zve32x and Zve64x extensions - 3 - --- 2024-03-28 Jason Chien New
[v3,1/3] target/riscv: Add support for Zve32x extension target/riscv: Support Zve32x and Zve64x extensions - 3 - --- 2024-03-28 Jason Chien New
[v2,5/5] target/riscv: Relax vector register check in RISCV gdbstub target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-25 Jason Chien New
[v2,4/5] target/riscv: Expose Zve64x extension to users target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-25 Jason Chien New
[v2,3/5] target/riscv: Add support for Zve64x extension target/riscv: Support Zve32x and Zve64x extensions - 3 - --- 2024-03-25 Jason Chien New
[v2,2/5] target/riscv: Expose Zve32x extension to users target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-25 Jason Chien New
[v2,1/5] target/riscv: Add support for Zve32x extension target/riscv: Support Zve32x and Zve64x extensions - 3 - --- 2024-03-25 Jason Chien New
[5/5] target/riscv: Relax vector register check in RISCV gdbstub target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-06 Jason Chien New
[4/5] target/riscv: Expose Zve64x extension to users target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-06 Jason Chien New
[3/5] target/riscv: Add support for Zve64x extension target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-06 Jason Chien New
[2/5] target/riscv: Expose Zve32x extension to users target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-06 Jason Chien New
[1/5] target/riscv: Add support for Zve32x extension target/riscv: Support Zve32x and Zve64x extensions - 2 - --- 2024-03-06 Jason Chien New
[v2] target/riscv: Update $ra with current $pc in trans_cm_jalt() [v2] target/riscv: Update $ra with current $pc in trans_cm_jalt() - 2 - --- 2024-02-07 Jason Chien New
target/riscv: Update $pc after linking to $ra in trans_cm_jalt() target/riscv: Update $pc after linking to $ra in trans_cm_jalt() - 1 - --- 2024-02-06 Jason Chien New
hw/pci-host: Allow extended config space access for Designware PCIe host hw/pci-host: Allow extended config space access for Designware PCIe host 1 1 - --- 2023-08-09 Jason Chien New
[2/2] hw/intc: Make rtc variable names consistent [1/2] hw/intc: Fix upper/lower mtime write calculation - 1 - --- 2023-07-28 Jason Chien New
[1/2] hw/intc: Fix upper/lower mtime write calculation [1/2] hw/intc: Fix upper/lower mtime write calculation - 1 - --- 2023-07-28 Jason Chien New
[RESEND,v3,1/1] target/riscv: Add Zihintntl extension ISA string to DTS target/riscv: Add Zihintntl extension ISA string to DTS - 2 - --- 2023-07-26 Jason Chien New
[v3,1/1] target/riscv: Add Zihintntl extension ISA string to DTS target/riscv: Add Zihintntl extension ISA string to DTS - 2 - --- 2023-07-11 Jason Chien New
[v2] target/riscv: Add Zihintntl extension ISA string to DTS [v2] target/riscv: Add Zihintntl extension ISA string to DTS - - - --- 2023-07-11 Jason Chien New
target/riscv: Add Zihintntl extension ISA string to DTS target/riscv: Add Zihintntl extension ISA string to DTS - 2 - --- 2023-07-04 Jason Chien New
[RFC] target/riscv: Add Zihintntl extension ISA string to DTS [RFC] target/riscv: Add Zihintntl extension ISA string to DTS - - - --- 2023-06-27 Jason Chien New
target/riscv: Set the correct exception for implict G-stage translation fail target/riscv: Set the correct exception for implict G-stage translation fail - 2 - --- 2023-06-27 Jason Chien New