Show patches with: Archived = No       |   3512 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v7,5/6] audio: Add functions to initialize buffers coreaudio fixes - 2 - --- 2025-01-24 Akihiko Odaki New
[v7,4/6] coreaudio: Commit the result of init in the end coreaudio fixes - - - --- 2025-01-24 Akihiko Odaki New
[v7,3/6] coreaudio: Improve naming coreaudio fixes - 2 - --- 2025-01-24 Akihiko Odaki New
[v7,2/6] coreaudio: Remove extra whitespaces coreaudio fixes - 1 - --- 2025-01-24 Akihiko Odaki New
[v7,1/6] coreaudio: Remove unnecessary explicit casts coreaudio fixes - - - --- 2025-01-24 Akihiko Odaki New
[v6,5/5] coreaudio: Initialize the buffer for device change coreaudio fixes 1 1 - --- 2025-01-24 Akihiko Odaki New
[v6,4/5] audio: Add functions to initialize buffers coreaudio fixes - 2 - --- 2025-01-24 Akihiko Odaki New
[v6,3/5] coreaudio: Commit the result of init in the end coreaudio fixes - - - --- 2025-01-24 Akihiko Odaki New
[v6,2/5] coreaudio: Improve naming coreaudio fixes - 1 - --- 2025-01-24 Akihiko Odaki New
[v6,1/5] coreaudio: Remove unnecessary explicit casts coreaudio fixes - - - --- 2025-01-24 Akihiko Odaki New
[v2,2/2] aspeed/wdt: Support software reset mode for AST2600 wdt/aspeed: Support software reset mode for AST2600 - 1 - --- 2025-01-24 Jamin Lin New
[v2,1/2] aspeed/wdt: Fix coding style wdt/aspeed: Support software reset mode for AST2600 - 1 - --- 2025-01-24 Jamin Lin New
[v2] hw/usb/hcd-ehci: Fix debug printf format string [v2] hw/usb/hcd-ehci: Fix debug printf format string - 1 - --- 2025-01-24 BALATON Zoltan New
[v1,4/4] x86-disas: add x86-mini disassembler implementation x86-disas: port x86-mini disassembler to QEMU - - - --- 2025-01-24 Michael Clark New
[v1,3/4] x86-disas: add x86-mini metadata tablegen script x86-disas: port x86-mini disassembler to QEMU - - - --- 2025-01-24 Michael Clark New
[v1,2/4] x86-disas: add x86-mini metadata documentation x86-disas: port x86-mini disassembler to QEMU - - - --- 2025-01-24 Michael Clark New
[v1,1/4] x86-disas: add x86-mini instruction set metadata x86-disas: port x86-mini disassembler to QEMU - - - --- 2025-01-24 Michael Clark New
[20/20] cpus: Build cpu_exec_[un]realizefn() methods once accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[19/20] cpus: Register VMState per user / system emulation accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[18/20] cpus: Have cpu_exec_initfn() per user / system emulation accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[17/20] cpus: Have cpu_class_init_props() per user / system emulation accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[16/20] cpus: Restrict cpu_common_post_load() code to TCG accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[15/20] cpus: Fix style in cpu-target.c accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[14/20] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c accel: Simplify cpu-target.c (omnibus) - - - --- 2025-01-23 Philippe Mathieu-Daudé New
[13/20] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[12/20] accel/accel-cpu-target.h: Include missing 'cpu.h' header accel: Simplify cpu-target.c (omnibus) 1 - - --- 2025-01-23 Philippe Mathieu-Daudé New
[11/20] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[10/20] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[09/20] accel/tcg: Restrict 'icount_align_option' global to TCG accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[08/20] accel/tcg: Restrict tlb_init() / destroy() to TCG accel: Simplify cpu-target.c (omnibus) - 2 - --- 2025-01-23 Philippe Mathieu-Daudé New
[07/20] accel/tcg: Build tcg_flags helpers as common code accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[06/20] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[05/20] cpus: Keep default fields initialization in cpu_common_initfn() accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[04/20] cpus: Cache CPUClass early in instance_init() handler accel: Simplify cpu-target.c (omnibus) - 1 - --- 2025-01-23 Philippe Mathieu-Daudé New
[03/20] gdbstub: Check for TCG before calling tb_flush() accel: Simplify cpu-target.c (omnibus) - 2 - --- 2025-01-23 Philippe Mathieu-Daudé New
[02/20] user: Extract common MMAP API to 'user/mmap.h' accel: Simplify cpu-target.c (omnibus) - 2 - --- 2025-01-23 Philippe Mathieu-Daudé New
[01/20] qemu/compiler: Absorb 'clang-tsa.h' accel: Simplify cpu-target.c (omnibus) - 3 - --- 2025-01-23 Philippe Mathieu-Daudé New
[v3] virtio-pci: correctly set virtio pci queue mem multiplier [v3] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-23 Srujana Challa Changes Requested
[v2] virtio-pci: correctly set virtio pci queue mem multiplier [v2] virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-20 Srujana Challa Changes Requested
virtio-pci: correctly set virtio pci queue mem multiplier virtio-pci: correctly set virtio pci queue mem multiplier - - - --- 2024-02-12 Srujana Challa Changes Requested
cryptodev-vhost-user: add asymmetric crypto support cryptodev-vhost-user: add asymmetric crypto support - - - --- 2023-05-14 Gowrishankar Muthukrishnan Superseded
[v1,2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v1,1/2] target/riscv: add Zicond as an experimental extension [v1,1/2] target/riscv: add Zicond as an experimental extension - - - --- 2023-01-20 Philipp Tomsich Superseded
[v3,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v3,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-24 Lev Kujawski Superseded
[v2,2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM 1 - - --- 2022-06-16 Lev Kujawski Superseded
[v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [v2,1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[2/2] tests/qtest/i440fx-test.c: Enable full test of i440FX PAM operation [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM [1/2] hw/pci-host/pam.c: Fully support RE^WE semantics of i440FX PAM - - - --- 2022-06-16 Lev Kujawski Superseded
[v1] error-report: fix g_date_time_format assertion [v1] error-report: fix g_date_time_format assertion - - - --- 2022-04-24 Wang, Haiyue Superseded
[v1] aio-posix: fix build failure io_uring 2.2 [v1] aio-posix: fix build failure io_uring 2.2 - - - --- 2022-02-17 Wang, Haiyue Superseded
[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v5,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 2 - --- 2022-01-31 Philipp Tomsich Superseded
[v4,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - - - --- 2022-01-30 Philipp Tomsich Superseded
[v4,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v4,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-30 Philipp Tomsich Superseded
[v3,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,6/7] target/riscv: Add XVentanaCondOps custom extension target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,5/7] target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,4/7] target/riscv: access cfg structure through DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,3/7] target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,2/7] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v3,1/7] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: Add XVentanaCondOps and supporting infrastructure changes - 1 - --- 2022-01-28 Philipp Tomsich Superseded
[v2,2/2] target/riscv: Add XVentanaCondOps custom extension [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v2,1/2] target/riscv: iterate over a table of decoders [v2,1/2] target/riscv: iterate over a table of decoders - - - --- 2022-01-13 Philipp Tomsich Superseded
[v1,2/2] target/riscv: Add XVentanaCondOps custom extension [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
[v1,1/2] decodetree: Add an optional predicate-function for decoding [v1,1/2] decodetree: Add an optional predicate-function for decoding - - - --- 2022-01-09 Philipp Tomsich Superseded
target/riscv: Fix position of 'experimental' comment target/riscv: Fix position of 'experimental' comment - 3 - --- 2022-01-06 Philipp Tomsich Accepted
[v10,16/16] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,13/16] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,12/16] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,10/16] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,09/16] target/riscv: Add instructions of the Zbc-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,08/16] target/riscv: Reassign instructions to the Zbs-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,06/16] target/riscv: Remove the W-form instructions from Zbs target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,05/16] target/riscv: Reassign instructions to the Zba-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 2 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) target/riscv: Update QEmu for Zb[abcs] 1.0.0 - - - --- 2021-09-04 Philipp Tomsich Superseded
[v10,02/16] target/riscv: fix clzw implementation to operate on arg1 target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v10,01/16] target/riscv: Introduce temporary in gen_add_uw() target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 3 - --- 2021-09-04 Philipp Tomsich Superseded
[v9,14/14] disas/riscv: Add Zb[abcs] instructions target/riscv: Update QEmu for Zb[abcs] 1.0.0 1 - - --- 2021-09-03 Philipp Tomsich Superseded
[v9,13/14] target/riscv: Remove RVB (replaced by Zb[abcs] target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,11/14] target/riscv: Add rev8 instruction, removing grev/grevi target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,10/14] target/riscv: Add a REQUIRE_32BIT macro target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
[v9,08/14] target/riscv: Reassign instructions to the Zbb-extension target/riscv: Update QEmu for Zb[abcs] 1.0.0 - 2 - --- 2021-09-03 Philipp Tomsich Superseded
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