diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index d631f74..b5e2256 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -148,6 +148,7 @@ void alpha_translate_init(void)
     done_init = 1;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     for (i = 0; i < 31; i++) {
         cpu_std_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b90b932..fa974b8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -87,6 +87,7 @@ void arm_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     for (i = 0; i < 16; i++) {
         cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 5ce5c58..8b34e38 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3362,6 +3362,7 @@ void cris_initialize_tcg(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cc_x = tcg_global_mem_new(TCG_AREG0,
                               offsetof(CPUCRISState, cc_x), "cc_x");
     cc_src = tcg_global_mem_new(TCG_AREG0,
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index df20bdc..c0adf29 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1249,6 +1249,7 @@ void cris_initialize_crisv10_tcg(void)
 	int i;
 
 	cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+        tcg_ctx.tcg_env = cpu_env;
 	cc_x = tcg_global_mem_new(TCG_AREG0,
 				  offsetof(CPUCRISState, cc_x), "cc_x");
 	cc_src = tcg_global_mem_new(TCG_AREG0,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 53a09f8..fe5e155 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7863,6 +7863,7 @@ void optimize_flags_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
                                        offsetof(CPUX86State, cc_op), "cc_op");
     cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index a333fc6..7cb786f 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1189,6 +1189,7 @@ void lm32_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
         cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d68d615..6280da0 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -91,6 +91,7 @@ void m68k_tcg_init(void)
                                                  "EXCEPTION");
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     p = cpu_reg_names;
     for (i = 0; i < 8; i++) {
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 3e3a49d..6a4be67 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1867,6 +1867,7 @@ void mb_tcg_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     env_debug = tcg_global_mem_new(TCG_AREG0, 
                     offsetof(CPUMBState, debug),
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 610ed7c..c3cdc63 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19818,6 +19818,7 @@ void mips_tcg_init(void)
         return;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     TCGV_UNUSED(cpu_gpr[0]);
     for (i = 1; i < 32; i++)
         cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index ab8f6a7..11277e0 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -109,6 +109,7 @@ void moxie_translate_init(void)
         return;
     }
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
                                     offsetof(CPUMoxieState, pc), "$pc");
     for (i = 0; i < 16; i++)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 3d29369..de2a541 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -77,6 +77,7 @@ void openrisc_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cpu_sr = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, sr), "sr");
     env_flags = tcg_global_mem_new_i32(TCG_AREG0,
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 204cb3a..1dff9b2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -85,6 +85,7 @@ void ppc_translate_init(void)
         return;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     p = cpu_reg_names;
     cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 262da89..8df75db 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -166,6 +166,7 @@ void s390x_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     psw_addr = tcg_global_mem_new_i64(TCG_AREG0,
                                       offsetof(CPUS390XState, psw.addr),
                                       "psw_addr");
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c3a8fbd..58d1624 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -98,6 +98,7 @@ void sh4_translate_init(void)
         return;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     for (i = 0; i < 24; i++)
         cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 44fdff8..981b628 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5357,6 +5357,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
         inited = 1;
 
         cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+        tcg_ctx.tcg_env = cpu_env;
         cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
                                              offsetof(CPUSPARCState, regwptr),
                                              "regwptr");
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index fb5413a..9ae6d72 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2440,6 +2440,7 @@ void tilegx_tcg_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
     for (i = 0; i < TILEGX_R_COUNT; i++) {
         cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 655db75..a56bf2c 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8366,6 +8366,7 @@ void tricore_tcg_init(void)
         return;
     }
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     /* reg init */
     for (i = 0 ; i < 16 ; i++) {
         cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 29c22f5..1c66ab2 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -72,6 +72,7 @@ void uc32_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
 
     for (i = 0; i < 32; i++) {
         cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index ce0f717..cbbed8d 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -217,6 +217,7 @@ void xtensa_translate_init(void)
     int i;
 
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+    tcg_ctx.tcg_env = cpu_env;
     cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
             offsetof(CPUXtensaState, pc), "pc");
 
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 8bed171..5f465bf 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -575,6 +575,10 @@ struct TCGContext {
 
     TBContext tb_ctx;
 
+    /* Track which vCPU triggers events */
+    CPUState *cpu;                      /* *_trans */
+    TCGv_cpu tcg_env;                   /* *_exec  */
+
     /* The TCGBackendData structure is private to tcg-target.c.  */
     struct TCGBackendData *be;
 
diff --git a/translate-all.c b/translate-all.c
index ecadb66..2395977 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1205,6 +1205,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     ti = profile_getclock();
 #endif
 
+    tcg_ctx.cpu = ENV_GET_CPU(env);
+
     tcg_func_start(&tcg_ctx);
 
     gen_intermediate_code(env, tb);
