From patchwork Mon Jan 18 15:25:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Kiarie X-Patchwork-Id: 8055421 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 366FC9F8AA for ; Mon, 18 Jan 2016 15:27:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6808F20489 for ; Mon, 18 Jan 2016 15:27:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6E8D720495 for ; Mon, 18 Jan 2016 15:27:10 +0000 (UTC) Received: from localhost ([::1]:60330 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLBi1-0002f6-RH for patchwork-qemu-devel@patchwork.kernel.org; Mon, 18 Jan 2016 10:27:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLBhr-0002cS-MP for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:27:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLBhn-0004FE-Gu for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:26:59 -0500 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:35560) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLBhn-0004F5-6y for qemu-devel@nongnu.org; Mon, 18 Jan 2016 10:26:55 -0500 Received: by mail-wm0-x244.google.com with SMTP id 123so10026169wmz.2 for ; Mon, 18 Jan 2016 07:26:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cuEIeROINkGDgxq4ZFvKB8OPxvGMfDmVBBMGbqqpQgY=; b=MYZWaRtztJwVBijSEy8CMQbsLhBCvZpMwJq6UexCds8X1y7cXR38NTltKXjJtuEQ8l urDHz8sbIzGl68EV0IPxD+GkUT3ung1qjyKiKD1KUlf75rNM9I4RlJeKKcaddIignSgQ WFcLdF/6zUE+7pxVA5efdN9JQXRE1i4VYbsmKCiyp+lyYjCwcObnO6F3tbWUpR4o+ZLV vOs8Kk/lmZcM9GiyS6SN2/8WOwBEn6DQWUtQ1zk1qO6WEFdQqiWD6HEpltP314LYDgd9 y1RIOCmrbKahXiyokg5KxoOQGqT6cUiTbmNd1vXbOtfZ1Uc9EX5tzawoBux0UoZFYhiw S83Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cuEIeROINkGDgxq4ZFvKB8OPxvGMfDmVBBMGbqqpQgY=; b=SYFcQPRBDI4VvFafexv2DPfSiOlNZhtD2lgFDFLKzvYWJP8evJwloe/2g6Gv+BXfg2 afIFE/GCHNxSVUMSjGzxMko2mUoTqtR6vdm+Z51B8c2rHEKIrZNy6mkLiggfZ0JgWChg kGEh+YcWrQNnRKqrdalhFRiFY/B3VLsTj4pu4VCju8g1d4gq4PCtAVB6SY9NryrZReLk qIQYP71cT2EDF1QPPG7dl7mLn5Dpw8UXCwe5NKqqStTvVRSvwmXBA6pt0sUPzYNirkq7 YdgaLWuh+A07sbLFHX3z4c2irCdGJYmrV78uE5Eg1f0IGmjeceD4qIIkEqKZZF/FNcs3 kfjQ== X-Gm-Message-State: AG10YOTC8OuE9cDe3k3Oxa/CtlkcCnLpSgJCgffaGubJ9jjBG1aEHZFvpDU8sEG1RjEwWQ== X-Received: by 10.28.19.204 with SMTP id 195mr14910956wmt.1.1453130814672; Mon, 18 Jan 2016 07:26:54 -0800 (PST) Received: from debian.flybox.orange ([154.122.88.181]) by smtp.googlemail.com with ESMTPSA id t3sm24381762wjz.11.2016.01.18.07.26.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jan 2016 07:26:54 -0800 (PST) From: David Kiarie To: qemu-devel@nongnu.org Date: Mon, 18 Jan 2016 18:25:44 +0300 Message-Id: <1453130745-25793-4-git-send-email-davidkiarie4@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1453130745-25793-1-git-send-email-davidkiarie4@gmail.com> References: <1453130745-25793-1-git-send-email-davidkiarie4@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::244 Cc: mst@redhat.com, crosthwaitepeter@gmail.com, valentine.sinitsyn@gmail.com, jan.kiszka@web.de, marcel@redhat.com, David Kiarie Subject: [Qemu-devel] [V4 3/4] hw/i386: ACPI table for AMD IO MMU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add IVRS table for AMD IO MMU. Signed-off-by: David Kiarie --- hw/i386/acpi-build.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ include/hw/acpi/acpi-defs.h | 55 +++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 78758e2..5c0d6b7 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -52,6 +52,7 @@ #include "hw/pci/pci_bus.h" #include "hw/pci-host/q35.h" #include "hw/i386/intel_iommu.h" +#include "hw/i386/amd_iommu.h" #include "hw/timer/hpet.h" #include "hw/acpi/aml-build.h" @@ -2424,6 +2425,70 @@ build_dmar_q35(GArray *table_data, GArray *linker) } static void +build_amd_iommu(GArray *table_data, GArray *linker) +{ + int iommu_start = table_data->len; + bool iommu_ambig; + + AcpiAMDIOMMUIVRS *ivrs; + AcpiAMDIOMMUHardwareUnit *iommu; + + /* IVRS definition */ + ivrs = acpi_data_push(table_data, sizeof(*ivrs)); + ivrs->revision = cpu_to_le16(ACPI_IOMMU_IVRS_TYPE); + ivrs->length = cpu_to_le16((sizeof(*ivrs) + sizeof(*iommu))); + ivrs->v_common_info = cpu_to_le64(AMD_IOMMU_HOST_ADDRESS_WIDTH << 8); + + AMDIOMMUState *s = (AMDIOMMUState *)object_resolve_path_type("", + TYPE_AMD_IOMMU_DEVICE, &iommu_ambig); + + /* IVDB definition */ + iommu = acpi_data_push(table_data, sizeof(*iommu)); + if (!iommu_ambig) { + iommu->type = cpu_to_le16(0x10); + /* IVHD flags */ + iommu->flags = cpu_to_le16(iommu->flags); + iommu->flags = cpu_to_le16(IVHD_HT_TUNEN | IVHD_PPRSUP | IVHD_IOTLBSUP + | IVHD_PREFSUP); + iommu->length = cpu_to_le16(sizeof(*iommu)); + iommu->device_id = cpu_to_le16(PCI_DEVICE_ID_RD890_IOMMU); + iommu->capability_offset = cpu_to_le16(s->capab_offset); + iommu->mmio_base = cpu_to_le64(s->mmio.addr); + iommu->pci_segment = 0; + iommu->interrupt_info = 0; + /* EFR features */ + iommu->efr_register = cpu_to_le64(IVHD_EFR_GTSUP | IVHD_EFR_HATS + | IVHD_EFR_GATS); + iommu->efr_register = cpu_to_le64(iommu->efr_register); + /* device entries */ + memset(iommu->dev_entries, 0, 20); + /* Add device flags here + * create entries for devices to be treated specially by IO MMU, + * currently we report all devices to IO MMU with no special flags + * DTE settings made here apply to all devices + * Refer to AMD IOMMU spec Table 97 + */ + iommu->dev_entries[12] = 3; + iommu->dev_entries[16] = 4; + iommu->dev_entries[17] = 0xff; + iommu->dev_entries[18] = 0xff; + } + + build_header(linker, table_data, (void *)(table_data->data + iommu_start), + "IVRS", table_data->len - iommu_start, 1, NULL); +} + +static bool acpi_has_amd_iommu(void) +{ + bool ambiguous; + Object *amd_iommu; + + amd_iommu = object_resolve_path_type("", TYPE_AMD_IOMMU_DEVICE, + &ambiguous); + return amd_iommu && !ambiguous; +} + +static void build_dsdt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc) { @@ -2691,6 +2756,11 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) build_dmar_q35(tables_blob, tables->linker); } + if (acpi_has_amd_iommu() && !acpi_has_iommu()) { + acpi_add_table(table_offsets, tables_blob); + build_amd_iommu(tables_blob, tables->linker); + } + if (acpi_has_nvdimm()) { nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); } diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index c7a03d4..a161358 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -570,4 +570,59 @@ typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; /* Masks for Flags field above */ #define ACPI_DMAR_INCLUDE_PCI_ALL 1 +/* IVRS constants */ +#define ACPI_IOMMU_HARDWAREUNIT_TYPE 0x10 +#define ACPI_IOMMU_IVRS_TYPE 0x1 +#define AMD_IOMMU_HOST_ADDRESS_WIDTH 39UL + +/* AMD IOMMU IVRS table */ +struct AcpiAMDIOMMUIVRS { + ACPI_TABLE_HEADER_DEF + uint32_t v_common_info; /* common virtualization information */ + uint64_t reserved; /* reserved */ +} QEMU_PACKED; +typedef struct AcpiAMDIOMMUIVRS AcpiAMDIOMMUIVRS; + +/* flags in the IVHD headers */ +#define IVHD_HT_TUNEN (1UL << 0) +#define IVHD_PASS_PW (1UL << 1) +#define IVHD_RESPASS_PW (1UL << 2) +#define IVHD_ISOC (1UL << 3) +#define IVHD_IOTLBSUP (1UL << 4) +#define IVHD_COHERENT (1UL << 5) +#define IVHD_PREFSUP (1UL << 6) +#define IVHD_PPRSUP (1UL << 7) + +/* features in the IVHD headers */ +#define IVHD_EFR_HATS 48 +#define IVHD_EFR_GATS 48 +#define IVHD_EFR_MSI_NUM +#define IVHD_EFR_PNBANKS +#define IVHD_EFR_PNCOUNTERS +#define IVHD_EFR_PASMAX +#define IVHD_EFR_HESUP (1UL << 7) +#define IVHD_EFR_GASUP (1UL << 6) +#define IVHD_EFR_IASUP (1UL << 5) +#define IVHD_EFR_GLXSUP (3UL << 3) +#define IVHD_EFR_GTSUP (1UL << 2) +#define IVHD_EFR_NXSUP (1UL << 1) +#define IVHD_EFR_XTSUP (1UL << 0) + +/* IVDB type 10h */ +struct AcpiAMDIOMMUHardwareUnit { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint64_t mmio_base; + uint16_t pci_segment; + uint16_t interrupt_info; + uint32_t features; + uint64_t efr_register; + uint64_t reserved; + uint8_t dev_entries[20]; +} QEMU_PACKED; +typedef struct AcpiAMDIOMMUHardwareUnit AcpiAMDIOMMUHardwareUnit; + #endif