From patchwork Mon Jan 25 10:02:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 8105851 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 39AA9BEEE5 for ; Mon, 25 Jan 2016 10:04:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89CD120306 for ; Mon, 25 Jan 2016 10:04:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DA81B202EB for ; Mon, 25 Jan 2016 10:04:19 +0000 (UTC) Received: from localhost ([::1]:36825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aNe0R-0005CP-8j for patchwork-qemu-devel@patchwork.kernel.org; Mon, 25 Jan 2016 05:04:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aNdzQ-0003fA-34 for qemu-devel@nongnu.org; Mon, 25 Jan 2016 05:03:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aNdzK-00059s-Ex for qemu-devel@nongnu.org; Mon, 25 Jan 2016 05:03:15 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:29499) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aNdzK-00059f-A7 for qemu-devel@nongnu.org; Mon, 25 Jan 2016 05:03:10 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id EF1AC9335952F for ; Mon, 25 Jan 2016 10:03:06 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Mon, 25 Jan 2016 10:03:09 +0000 From: Leon Alrae To: Date: Mon, 25 Jan 2016 10:02:34 +0000 Message-ID: <1453716155-9492-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1453716155-9492-1-git-send-email-leon.alrae@imgtec.com> References: <1453716155-9492-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: Miodrag Dinic Subject: [Qemu-devel] [PULL 3/4] target-mips: Fix ALIGN instruction when bp=0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Miodrag Dinic If executing ALIGN with shift count bp=0 within mips64 emulation, the result of the operation should be sign extended. Taken from the official documentation (pseudo code) : ALIGN: tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp) tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp)) tmp = tmp_rt_hi || tmp_rt_lo GPR[rd] = sign_extend.32(tmp) Signed-off-by: Miodrag Dinic Reviewed-by: Aurelien Jarno Reviewed-by: Leon Alrae Signed-off-by: Leon Alrae --- target-mips/translate.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 5626647..d2443d3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4630,7 +4630,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, t0 = tcg_temp_new(); gen_load_gpr(t0, rt); if (bp == 0) { - tcg_gen_mov_tl(cpu_gpr[rd], t0); + switch (opc) { + case OPC_ALIGN: + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DALIGN: + tcg_gen_mov_tl(cpu_gpr[rd], t0); + break; +#endif + } } else { TCGv t1 = tcg_temp_new(); gen_load_gpr(t1, rs);