From patchwork Tue Jan 26 21:44:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Christophe Dubois X-Patchwork-Id: 8127831 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C7F0ABEEE5 for ; Tue, 26 Jan 2016 21:45:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F2B502024F for ; Tue, 26 Jan 2016 21:45:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CFFF92024D for ; Tue, 26 Jan 2016 21:45:25 +0000 (UTC) Received: from localhost ([::1]:47045 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBQT-0005V5-7J for patchwork-qemu-devel@patchwork.kernel.org; Tue, 26 Jan 2016 16:45:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBQ7-0005CG-Hs for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:45:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOBQ5-0004SR-QW for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:45:03 -0500 Received: from zose-mta02.web4all.fr ([185.49.20.43]:36794) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOBQ5-0004SK-HS for qemu-devel@nongnu.org; Tue, 26 Jan 2016 16:45:01 -0500 Received: from localhost (localhost [127.0.0.1]) by zose-mta02.web4all.fr (Postfix) with ESMTP id F331F445DA; Tue, 26 Jan 2016 22:45:00 +0100 (CET) Received: from zose-mta02.web4all.fr ([127.0.0.1]) by localhost (zose-mta02.web4all.fr [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id dEN0r-l8BKnA; Tue, 26 Jan 2016 22:45:00 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zose-mta02.web4all.fr (Postfix) with ESMTP id 5ACF7445E4; Tue, 26 Jan 2016 22:45:00 +0100 (CET) X-Virus-Scanned: amavisd-new at zose-mta-02.w4a.fr Received: from zose-mta02.web4all.fr ([127.0.0.1]) by localhost (zose-mta02.web4all.fr [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id oKToXimGlubr; Tue, 26 Jan 2016 22:45:00 +0100 (CET) Received: from localhost.localdomain (smm49-1-78-235-240-156.fbx.proxad.net [78.235.240.156]) by zose-mta02.web4all.fr (Postfix) with ESMTPSA id 0EB89445DA; Tue, 26 Jan 2016 22:45:00 +0100 (CET) From: Jean-Christophe Dubois To: qemu-devel@nongnu.org, peter.maydell@linaro.org, rosthwaite.peter@gmail.com Date: Tue, 26 Jan 2016 22:44:58 +0100 Message-Id: <1453844698-26375-1-git-send-email-jcd@tribudubois.net> X-Mailer: git-send-email 2.5.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 185.49.20.43 Cc: Jean-Christophe Dubois Subject: [Qemu-devel] [PATCH 2/6] i.MX: simplify CCM to only handle clock required by timers. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Various i.MX timers (GPT, EPIT, PWM, ...) are only requesting 4 clocks from the system. * CLK_NONE, * CLK_IPG, * CLK_IPG_HIGH, * CLK_32k Other "clocks" are not required by the qemu framework so far. Signed-off-by: Jean-Christophe Dubois --- hw/misc/imx25_ccm.c | 35 +++++------------------------------ hw/misc/imx31_ccm.c | 38 ++++---------------------------------- hw/timer/imx_epit.c | 8 ++++---- hw/timer/imx_gpt.c | 16 ++++++++-------- include/hw/misc/imx_ccm.h | 10 ++-------- 5 files changed, 23 insertions(+), 84 deletions(-) diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c index 23759ca..38599f2 100644 --- a/hw/misc/imx25_ccm.c +++ b/hw/misc/imx25_ccm.c @@ -119,20 +119,6 @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev) return freq; } -static uint32_t imx25_ccm_get_upll_clk(IMXCCMState *dev) -{ - uint32_t freq = 0; - IMX25CCMState *s = IMX25_CCM(dev); - - if (!EXTRACT(s->reg[IMX25_CCM_CCTL_REG], UPLL_DIS)) { - freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_UPCTL_REG], CKIH_FREQ); - } - - DPRINTF("freq = %d\n", freq); - - return freq; -} - static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev) { uint32_t freq; @@ -181,21 +167,10 @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) DPRINTF("Clock = %d)\n", clock); switch (clock) { - case NOCLK: - break; - case CLK_MPLL: - freq = imx25_ccm_get_mpll_clk(dev); - break; - case CLK_UPLL: - freq = imx25_ccm_get_upll_clk(dev); - break; - case CLK_MCU: - freq = imx25_ccm_get_mcu_clk(dev); - break; - case CLK_AHB: - freq = imx25_ccm_get_ahb_clk(dev); + case CLK_NONE: break; case CLK_IPG: + case CLK_IPG_HIGH: freq = imx25_ccm_get_ipg_clk(dev); break; case CLK_32k: @@ -221,9 +196,9 @@ static void imx25_ccm_reset(DeviceState *dev) memset(s->reg, 0, IMX25_CCM_MAX_REG * sizeof(uint32_t)); s->reg[IMX25_CCM_MPCTL_REG] = 0x800b2c01; s->reg[IMX25_CCM_UPCTL_REG] = 0x84042800; - /* + /* * The value below gives: - * CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz. + * CPU = 133 MHz, AHB = 66,5 MHz, IPG = 33 MHz. */ s->reg[IMX25_CCM_CCTL_REG] = 0xd0030000; s->reg[IMX25_CCM_CGCR0_REG] = 0x028A0100; @@ -240,7 +215,7 @@ static void imx25_ccm_reset(DeviceState *dev) /* * default boot will change the reset values to allow: - * CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz. + * CPU = 399 MHz, AHB = 133 MHz, IPG = 66,5 MHz. * For some reason, this doesn't work. With the value below, linux * detects a 88 MHz IPG CLK instead of 66,5 MHz. s->reg[IMX25_CCM_CCTL_REG] = 0x20032000; diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c index 47d6ead..3876cc2 100644 --- a/hw/misc/imx31_ccm.c +++ b/hw/misc/imx31_ccm.c @@ -111,7 +111,7 @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev) if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) { freq *= 1024; } - } + } } else { freq = CKIH_FREQ; } @@ -134,6 +134,7 @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev) return freq; } + static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev) { uint32_t freq; @@ -151,32 +152,6 @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev) return freq; } -static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev) -{ - uint32_t freq; - IMX31CCMState *s = IMX31_CCM(dev); - - freq = imx31_ccm_get_mcu_main_clk(dev) - / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU)); - - DPRINTF("freq = %d\n", freq); - - return freq; -} - -static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev) -{ - uint32_t freq; - IMX31CCMState *s = IMX31_CCM(dev); - - freq = imx31_ccm_get_mcu_main_clk(dev) - / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP)); - - DPRINTF("freq = %d\n", freq); - - return freq; -} - static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev) { uint32_t freq; @@ -208,15 +183,10 @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) uint32_t freq = 0; switch (clock) { - case NOCLK: - break; - case CLK_MCU: - freq = imx31_ccm_get_mcu_clk(dev); - break; - case CLK_HSP: - freq = imx31_ccm_get_hsp_clk(dev); + case CLK_NONE: break; case CLK_IPG: + case CLK_IPG_HIGH: freq = imx31_ccm_get_ipg_clk(dev); break; case CLK_32k: diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 50bf83c..a67bcb5 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -51,10 +51,10 @@ static char const *imx_epit_reg_name(uint32_t reg) * These are typical. */ static const IMXClk imx_epit_clocks[] = { - NOCLK, /* 00 disabled */ - CLK_IPG, /* 01 ipg_clk, ~532MHz */ - CLK_IPG, /* 10 ipg_clk_highfreq */ - CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ + CLK_NONE, /* 00 disabled */ + CLK_IPG, /* 01 ipg_clk, ~532MHz */ + CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ + CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ }; /* diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index b227256..b2f03b0 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -80,14 +80,14 @@ static const VMStateDescription vmstate_imx_timer_gpt = { }; static const IMXClk imx_gpt_clocks[] = { - NOCLK, /* 000 No clock source */ - CLK_IPG, /* 001 ipg_clk, 532MHz*/ - CLK_IPG, /* 010 ipg_clk_highfreq */ - NOCLK, /* 011 not defined */ - CLK_32k, /* 100 ipg_clk_32k */ - NOCLK, /* 101 not defined */ - NOCLK, /* 110 not defined */ - NOCLK, /* 111 not defined */ + CLK_NONE, /* 000 No clock source */ + CLK_IPG, /* 001 ipg_clk, 532MHz*/ + CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ + CLK_NONE, /* 011 not defined */ + CLK_32k, /* 100 ipg_clk_32k */ + CLK_NONE, /* 101 not defined */ + CLK_NONE, /* 110 not defined */ + CLK_NONE, /* 111 not defined */ }; static void imx_gpt_set_freq(IMXGPTState *s) diff --git a/include/hw/misc/imx_ccm.h b/include/hw/misc/imx_ccm.h index 5c4b795..48a7afa 100644 --- a/include/hw/misc/imx_ccm.h +++ b/include/hw/misc/imx_ccm.h @@ -43,15 +43,9 @@ typedef struct IMXCCMState { } IMXCCMState; typedef enum { - NOCLK, - CLK_MPLL, - CLK_UPLL, - CLK_MCU, - CLK_HSP, - CLK_MAX, - CLK_AHB, + CLK_NONE, CLK_IPG, - CLK_PER, + CLK_IPG_HIGH, CLK_32k } IMXClk;