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[131.111.184.8]) by smtp.gmail.com with ESMTPSA id n5sm8685996wmf.3.2016.01.29.10.40.37 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Jan 2016 10:40:37 -0800 (PST) From: James Clarke To: qemu-devel@nongnu.org Date: Fri, 29 Jan 2016 18:40:20 +0000 Message-Id: <1454092821-46795-2-git-send-email-jrtc27@jrtc27.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454092821-46795-1-git-send-email-jrtc27@jrtc27.com> References: <1454092821-46795-1-git-send-email-jrtc27@jrtc27.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::242 Cc: James Clarke , qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Subject: [Qemu-devel] [PATCH v2 1/2] target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: James Clarke --- target-ppc/cpu.h | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9706000..3a967b7 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -686,24 +686,37 @@ enum { #define FP_FX (1ull << FPSCR_FX) #define FP_FEX (1ull << FPSCR_FEX) +#define FP_VX (1ull << FPSCR_VX) #define FP_OX (1ull << FPSCR_OX) -#define FP_OE (1ull << FPSCR_OE) #define FP_UX (1ull << FPSCR_UX) -#define FP_UE (1ull << FPSCR_UE) -#define FP_XX (1ull << FPSCR_XX) -#define FP_XE (1ull << FPSCR_XE) #define FP_ZX (1ull << FPSCR_ZX) -#define FP_ZE (1ull << FPSCR_ZE) -#define FP_VX (1ull << FPSCR_VX) +#define FP_XX (1ull << FPSCR_XX) #define FP_VXSNAN (1ull << FPSCR_VXSNAN) #define FP_VXISI (1ull << FPSCR_VXISI) -#define FP_VXIMZ (1ull << FPSCR_VXIMZ) -#define FP_VXZDZ (1ull << FPSCR_VXZDZ) #define FP_VXIDI (1ull << FPSCR_VXIDI) +#define FP_VXZDZ (1ull << FPSCR_VXZDZ) +#define FP_VXIMZ (1ull << FPSCR_VXIMZ) #define FP_VXVC (1ull << FPSCR_VXVC) +#define FP_FR (1ull << FSPCR_FR) +#define FP_FI (1ull << FPSCR_FI) +#define FP_C (1ull << FPSCR_C) +#define FP_FL (1ull << FPSCR_FL) +#define FP_FG (1ull << FPSCR_FG) +#define FP_FE (1ull << FPSCR_FE) +#define FP_FU (1ull << FPSCR_FU) +#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU) +#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU) +#define FP_VXSOFT (1ull << FPSCR_VXSOFT) +#define FP_VXSQRT (1ull << FPSCR_VXSQRT) #define FP_VXCVI (1ull << FPSCR_VXCVI) #define FP_VE (1ull << FPSCR_VE) -#define FP_FI (1ull << FPSCR_FI) +#define FP_OE (1ull << FPSCR_OE) +#define FP_UE (1ull << FPSCR_UE) +#define FP_ZE (1ull << FPSCR_ZE) +#define FP_XE (1ull << FPSCR_XE) +#define FP_NI (1ull << FPSCR_NI) +#define FP_RN1 (1ull << FPSCR_RN1) +#define FP_RN (1ull << FPSCR_RN) /*****************************************************************************/ /* Vector status and control register */