diff mbox

target-arm: Don't report presence of EL2 if it doesn't exist

Message ID 1454437242-10262-1-git-send-email-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Peter Maydell Feb. 2, 2016, 6:20 p.m. UTC
We already modify the processor feature bits to not report EL3
support to the guest if EL3 isn't enabled for the CPU we're emulating.
Add similar support for not reporting EL2 unless it is enabled.
This is necessary because real world guest code running at EL3
(trusted firmware or bootloaders) will query the ID registers to
determine whether it should start a guest Linux kernel in EL2 or EL3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
When full EL2 arrives and we have the CPU property for it then
this will expand a bit to look like the 'if (!cpu->has_el3)'
condition just above it.

 target-arm/cpu.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Sergey Fedorov Feb. 3, 2016, 12:30 p.m. UTC | #1
On 02.02.2016 21:20, Peter Maydell wrote:
> We already modify the processor feature bits to not report EL3
> support to the guest if EL3 isn't enabled for the CPU we're emulating.
> Add similar support for not reporting EL2 unless it is enabled.
> This is necessary because real world guest code running at EL3
> (trusted firmware or bootloaders) will query the ID registers to
> determine whether it should start a guest Linux kernel in EL2 or EL3.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>

> ---
> When full EL2 arrives and we have the CPU property for it then
> this will expand a bit to look like the 'if (!cpu->has_el3)'
> condition just above it.
>
>  target-arm/cpu.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 6c34476..0cc075d 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -650,6 +650,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
>          cpu->id_aa64pfr0 &= ~0xf000;
>      }
>  
> +    if (!arm_feature(env, ARM_FEATURE_EL2)) {
> +        /* Disable the hypervisor feature bits in the processor feature
> +         * registers if we don't have EL2. These are id_pfr1[15:12] and
> +         * id_aa64pfr0_el1[11:8].
> +         */
> +        cpu->id_aa64pfr0 &= ~0xf00;
> +        cpu->id_pfr1 &= ~0xf000;
> +    }
> +
>      if (!cpu->has_mpu) {
>          unset_feature(env, ARM_FEATURE_MPU);
>      }
diff mbox

Patch

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6c34476..0cc075d 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -650,6 +650,15 @@  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->id_aa64pfr0 &= ~0xf000;
     }
 
+    if (!arm_feature(env, ARM_FEATURE_EL2)) {
+        /* Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2. These are id_pfr1[15:12] and
+         * id_aa64pfr0_el1[11:8].
+         */
+        cpu->id_aa64pfr0 &= ~0xf00;
+        cpu->id_pfr1 &= ~0xf000;
+    }
+
     if (!cpu->has_mpu) {
         unset_feature(env, ARM_FEATURE_MPU);
     }