From patchwork Wed Feb 3 16:56:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 8205411 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 534A2BEEE5 for ; Wed, 3 Feb 2016 16:59:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC1702022D for ; Wed, 3 Feb 2016 16:59:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E803D201ED for ; Wed, 3 Feb 2016 16:59:49 +0000 (UTC) Received: from localhost ([::1]:36266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR0mT-0006kD-Af for patchwork-qemu-devel@patchwork.kernel.org; Wed, 03 Feb 2016 11:59:49 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR0k9-00039p-7x for qemu-devel@nongnu.org; Wed, 03 Feb 2016 11:57:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aR0k5-0005ut-3N for qemu-devel@nongnu.org; Wed, 03 Feb 2016 11:57:25 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:47970) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR0k4-0005um-6u for qemu-devel@nongnu.org; Wed, 03 Feb 2016 11:57:21 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 54E791F3F956B; Wed, 3 Feb 2016 16:57:16 +0000 (GMT) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 16:57:18 +0000 From: Leon Alrae To: Date: Wed, 3 Feb 2016 16:56:44 +0000 Message-ID: <1454518611-26134-3-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1454518611-26134-1-git-send-email-leon.alrae@imgtec.com> References: <1454518611-26134-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 2/9] hw/mips: add ITC Storage Cells X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define single structure for FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell contains a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c | 17 +++++++++++++++++ include/hw/misc/mips_itu.h | 25 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index cf79bc6..d6f6905 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -116,6 +116,20 @@ static const MemoryRegionOps itc_storage_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static void itc_reset_cells(MIPSITUState *s) +{ + int i; + int num_cell = get_num_cells(s); + + memset(s->cell, 0, num_cell * sizeof(s->cell[0])); + + for (i = 0; i < s->num_fifo; i++) { + s->cell[i].tag.E = 1; + s->cell[i].tag.FIFO = 1; + s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT; + } +} + static void mips_itu_init(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); @@ -151,6 +165,9 @@ static void mips_itu_realize(DeviceState *dev, Error **errp) ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) | (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS); + s->cell = g_new(ITCStorageCell, get_num_cells(s)); + itc_reset_cells(s); + memory_region_set_enabled(&s->storage_io, false); } diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 9ddd8b4..b3a4532 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -23,6 +23,30 @@ #define TYPE_MIPS_ITU "mips-itu" #define MIPS_ITU(obj) OBJECT_CHECK(MIPSITUState, (obj), TYPE_MIPS_ITU) +#define ITC_CELL_DEPTH_SHIFT 2 +#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT) + +typedef struct ITCStorageCell { + struct { + uint8_t FIFODepth; /* Log2 of the cell depth */ + uint8_t FIFOPtr; /* Number of elements in a FIFO cell */ + uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */ + uint8_t T; /* Trap Bit */ + uint8_t F; /* Full Bit */ + uint8_t E; /* Empty Bit */ + } tag; + + /* Index of the oldest element in the queue */ + uint8_t fifo_out; + + /* Circular buffer for FIFO. Semaphore cells use index 0 only */ + uint64_t data[ITC_CELL_DEPTH]; + + /* Bitmap tracking blocked threads on the cell. + TODO: support >64 threads ? */ + uint64_t blocked_threads; +} ITCStorageCell; + #define ITC_ADDRESSMAP_NUM 2 typedef struct MIPSITUState { @@ -34,6 +58,7 @@ typedef struct MIPSITUState { int32_t num_semaphores; /* ITC Storage */ + ITCStorageCell *cell; MemoryRegion storage_io; /* ITC Configuration Tags */