| Message ID | 1454690704-16233-7-git-send-email-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05.02.2016 19:45, Peter Maydell wrote: > If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, > this should be reported with a syndrome register indicating an > FP access trap, not one indicating a system register access trap. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> > --- > target-arm/cpu.h | 5 +++++ > target-arm/helper.c | 4 ++-- > target-arm/op_helper.c | 13 +++++++++++++ > 3 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index d1d6886..a959ad6 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1322,6 +1322,11 @@ typedef enum CPAccessResult { > /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ > CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, > CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, > + /* Access fails and results in an exception syndrome for an FP access, > + * trapped directly to EL2 or EL3 > + */ > + CP_ACCESS_TRAP_FP_EL2 = 7, > + CP_ACCESS_TRAP_FP_EL3 = 8, > } CPAccessResult; > > /* Access functions for coprocessor registers. These cannot fail and > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 064b415..163a72a 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3012,10 +3012,10 @@ static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, > bool isread) > { > if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { > - return CP_ACCESS_TRAP_EL2; > + return CP_ACCESS_TRAP_FP_EL2; > } > if (env->cp15.cptr_el[3] & CPTR_TFP) { > - return CP_ACCESS_TRAP_EL3; > + return CP_ACCESS_TRAP_FP_EL3; > } > return CP_ACCESS_OK; > } > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 4fedae5..754f080 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -500,6 +500,19 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, > target_el = 3; > syndrome = syn_uncategorized(); > break; > + case CP_ACCESS_TRAP_FP_EL2: > + target_el = 2; > + /* Since we are an implementation that takes exceptions on a trapped > + * conditional insn only if the insn has passed its condition code > + * check, we take the IMPDEF choice to always report CV=1 COND=0xe > + * (which is also the required value for AArch64 traps). > + */ > + syndrome = syn_fp_access_trap(1, 0xe, false); > + break; > + case CP_ACCESS_TRAP_FP_EL3: > + target_el = 3; > + syndrome = syn_fp_access_trap(1, 0xe, false); > + break; > default: > g_assert_not_reached(); > }
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d1d6886..a959ad6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1322,6 +1322,11 @@ typedef enum CPAccessResult { /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5, CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6, + /* Access fails and results in an exception syndrome for an FP access, + * trapped directly to EL2 or EL3 + */ + CP_ACCESS_TRAP_FP_EL2 = 7, + CP_ACCESS_TRAP_FP_EL3 = 8, } CPAccessResult; /* Access functions for coprocessor registers. These cannot fail and diff --git a/target-arm/helper.c b/target-arm/helper.c index 064b415..163a72a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3012,10 +3012,10 @@ static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { - return CP_ACCESS_TRAP_EL2; + return CP_ACCESS_TRAP_FP_EL2; } if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_EL3; + return CP_ACCESS_TRAP_FP_EL3; } return CP_ACCESS_OK; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 4fedae5..754f080 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -500,6 +500,19 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = 3; syndrome = syn_uncategorized(); break; + case CP_ACCESS_TRAP_FP_EL2: + target_el = 2; + /* Since we are an implementation that takes exceptions on a trapped + * conditional insn only if the insn has passed its condition code + * check, we take the IMPDEF choice to always report CV=1 COND=0xe + * (which is also the required value for AArch64 traps). + */ + syndrome = syn_fp_access_trap(1, 0xe, false); + break; + case CP_ACCESS_TRAP_FP_EL3: + target_el = 3; + syndrome = syn_fp_access_trap(1, 0xe, false); + break; default: g_assert_not_reached(); }
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/cpu.h | 5 +++++ target-arm/helper.c | 4 ++-- target-arm/op_helper.c | 13 +++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-)