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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id 1sm49669183pfm.10.2016.02.09.02.40.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Feb 2016 02:40:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 9 Feb 2016 21:40:00 +1100 Message-Id: <1455014403-10742-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1455014403-10742-1-git-send-email-rth@twiddle.net> References: <1455014403-10742-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c00::243 Cc: james.hogan@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 12/15] tcg-mips: Use mips64r6 instructions in tcg_out_ldst X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DAUI, DAHI, and DATI insns can be used to eliminate one extra instruction in these cases. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index f7f4331..bda31c2 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -422,6 +422,7 @@ typedef enum { /* Aliases for convenience. */ ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, + ALIAS_PAUI = sizeof(void *) == 4 ? OPC_AUI : OPC_DAUI, ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 ? OPC_SRL : OPC_DSRL, } MIPSInsn; @@ -779,9 +780,48 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) } } +static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph, + TCGReg reg0, TCGReg reg1, tcg_target_long ofs) +{ + TCGReg scratch = TCG_TMP0; + int16_t lo = ofs; + int32_t hi = ofs - lo; + + ofs = ofs - hi - lo; + if (oph == OPC_DAUI && ofs != 0) { + tcg_target_long tmp; + + /* Bits are set in the high 32-bit half. Thus we require th + use of DAHI and/or DATI. The R6 manual recommends addition + of immediates in order of mid to high (DAUI, DAHI, DATI, OPL) + in order to simplify hardware recognizing these sequences. */ + + tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16); + + tmp = ofs >> 16 >> 16; + if (tmp & 0xffff) { + tcg_out_opc_imm(s, OPC_DAHI, scratch, 0, tmp); + } + tmp = (tmp - (int16_t)tmp) >> 16; + if (tmp) { + tcg_out_opc_imm(s, OPC_DATI, scratch, 0, tmp); + } + reg1 = scratch; + } else if (hi != 0) { + tcg_out_opc_imm(s, oph, scratch, reg1, hi >> 16); + reg1 = scratch; + } + tcg_out_opc_imm(s, opc, reg0, reg1, lo); +} + static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, TCGReg addr, intptr_t ofs) { + if (use_mips32r6_instructions) { + tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs); + return; + } + int16_t lo = ofs; if (ofs != lo) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);