From patchwork Tue Feb 23 16:05:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 8394011 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 966FAC0553 for ; Tue, 23 Feb 2016 16:06:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B05AF202F8 for ; Tue, 23 Feb 2016 16:06:37 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9FD97202E9 for ; Tue, 23 Feb 2016 16:06:36 +0000 (UTC) Received: from localhost ([::1]:58096 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYFTv-0004mI-Ta for patchwork-qemu-devel@patchwork.kernel.org; Tue, 23 Feb 2016 11:06:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYFTd-0004eg-7l for qemu-devel@nongnu.org; Tue, 23 Feb 2016 11:06:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYFTW-000325-MC for qemu-devel@nongnu.org; Tue, 23 Feb 2016 11:06:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:40583) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYFTW-00031w-CF for qemu-devel@nongnu.org; Tue, 23 Feb 2016 11:06:10 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (Postfix) with ESMTPS id 10DCC552E6; Tue, 23 Feb 2016 16:06:10 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u1NG63qP019433; Tue, 23 Feb 2016 11:06:07 -0500 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Tue, 23 Feb 2016 17:05:54 +0100 Message-Id: <1456243560-67516-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1456243560-67516-1-git-send-email-imammedo@redhat.com> References: <1456243560-67516-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: ehabkost@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com, Paolo Bonzini , afaerber@suse.de, Richard Henderson Subject: [Qemu-devel] [PATCH v3 2/8] cpu: introduce possible-cpus interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP on x86 currently range 0..max_cpus is used to generate architecture-dependent CPU ID (APIC Id) for each present and possible CPUs. However architecture-dependent CPU IDs list could be sparse and code that needs to enumerate all IDs (ACPI) ended up doing guess work enumerating all possible and impossible IDs up to apic_id_limit = x86_cpu_apic_id_from_index(max_cpus). That leads to creation of MADT/SRAT entries and Processor objects in ACPI tables for not possible CPUs. Fix it by allowing board specify a concrete list of CPU IDs accourding its own rules (which for x86 depends on topology). So that code that needs this list could request it from board instead of trying to figure out what IDs are correct on its own. This interface will also allow to help making AML part of CPU hotplug target independent so it could be reused for ARM target. Signed-off-by: Igor Mammedov CC: afaerber@suse.de --- hw/i386/pc.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- include/hw/boards.h | 1 + include/hw/i386/pc.h | 1 + include/qom/cpu.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ qom/cpu.c | 7 +++++++ 5 files changed, 98 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 151a64c..bfc5bae 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1132,10 +1132,17 @@ void pc_cpus_init(PCMachineState *pcms) exit(1); } - for (i = 0; i < smp_cpus; i++) { - cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), - &error_fatal); - object_unref(OBJECT(cpu)); + pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * (max_cpus - 1)); + for (i = 0; i < max_cpus; i++) { + pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); + pcms->possible_cpus->len++; + if (i < smp_cpus) { + cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), + &error_fatal); + pcms->possible_cpus->cpus[i].cpu = CPU(cpu); + object_unref(OBJECT(cpu)); + } } /* tell smbios about cpuid version and features */ @@ -1658,9 +1665,19 @@ static void pc_dimm_unplug(HotplugHandler *hotplug_dev, error_propagate(errp, local_err); } +static int pc_apic_cmp(const void *a, const void *b) +{ + CPUArchId *apic_a = (CPUArchId *)a; + CPUArchId *apic_b = (CPUArchId *)b; + + return apic_a->arch_id - apic_b->arch_id; +} + static void pc_cpu_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + CPUClass *cc = CPU_GET_CLASS(dev); + CPUArchId apic_id, *found_cpu; HotplugHandlerClass *hhc; Error *local_err = NULL; PCMachineState *pcms = PC_MACHINE(hotplug_dev); @@ -1683,6 +1700,13 @@ static void pc_cpu_plug(HotplugHandler *hotplug_dev, /* increment the number of CPUs */ rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); + + apic_id.arch_id = cc->get_arch_id(CPU(dev)); + found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, + pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), + pc_apic_cmp); + assert(found_cpu); + found_cpu->cpu = CPU(dev); out: error_propagate(errp, local_err); } @@ -1925,11 +1949,23 @@ static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) return topo.pkg_id; } +static CPUArchIdList *pc_get_possible_cpus_list(PossibleCpus *pcs) +{ + PCMachineState *pcms = PC_MACHINE(pcs); + int len = sizeof(CPUArchIdList) + + sizeof(CPUArchId) * (pcms->possible_cpus->len - 1); + CPUArchIdList *list = g_malloc(len); + + memcpy(list, pcms->possible_cpus, len); + return list; +} + static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); + PossibleCpusClass *psc = POSSIBLE_CPUS_CLASS(oc); pcmc->get_hotplug_handler = mc->get_hotplug_handler; pcmc->pci_enabled = true; @@ -1954,6 +1990,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) hc->plug = pc_machine_device_plug_cb; hc->unplug_request = pc_machine_device_unplug_request_cb; hc->unplug = pc_machine_device_unplug_cb; + psc->get_possible_cpus_list = pc_get_possible_cpus_list; } static const TypeInfo pc_machine_info = { @@ -1966,6 +2003,7 @@ static const TypeInfo pc_machine_info = { .class_init = pc_machine_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, + { TYPE_POSSIBLE_CPUS }, { } }, }; diff --git a/include/hw/boards.h b/include/hw/boards.h index 0f30959..90a9d15 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -8,6 +8,7 @@ #include "sysemu/accel.h" #include "hw/qdev.h" #include "qom/object.h" +#include "qom/cpu.h" void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, const char *name, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 8b3546e..3e09232 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -65,6 +65,7 @@ struct PCMachineState { /* CPU and apic information: */ bool apic_xrupt_override; unsigned apic_id_limit; + CPUArchIdList *possible_cpus; /* NUMA information: */ uint64_t numa_nodes; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index ff54600..eedd3f2 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -837,4 +837,51 @@ extern const struct VMStateDescription vmstate_cpu_common; .offset = 0, \ } +#define TYPE_POSSIBLE_CPUS "possible-cpus" + +#define POSSIBLE_CPUS_CLASS(klass) \ + OBJECT_CLASS_CHECK(PossibleCpusClass, (klass), \ + TYPE_POSSIBLE_CPUS) +#define POSSIBLE_CPUS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PossibleCpusClass, (obj), \ + TYPE_POSSIBLE_CPUS) +#define POSSIBLE_CPUS(obj) \ + INTERFACE_CHECK(PossibleCpus, (obj), \ + TYPE_POSSIBLE_CPUS) + +typedef struct PossibleCpus { + /* */ + Object Parent; +} PossibleCpus; + +/** + * CPUArchId: + * @arch_id - architecture-dependent CPU ID of present or possible CPU + * @cpu - pointer to corresponding CPU object ii it's present on NULL otherwise + */ +typedef struct { + uint64_t arch_id; + struct CPUState *cpu; +} CPUArchId; + +typedef struct { + int len; + CPUArchId cpus[1]; +} CPUArchIdList; + +/** + * PossibleCpusClass: + * @get_possible_cpus_list: + * Returns asorted by arch_id array of possible CPUs, + * which includes CPU IDs for present and possible to hotplug CPUs. + * Caller is responsible for freeing returned list. + */ +typedef struct PossibleCpusClass { + /* */ + InterfaceClass parent_class; + + /* */ + CPUArchIdList *(*get_possible_cpus_list)(PossibleCpus *pcs); +} PossibleCpusClass; + #endif diff --git a/qom/cpu.c b/qom/cpu.c index aeb32f1..8e9968f 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -384,9 +384,16 @@ static const TypeInfo cpu_type_info = { .class_init = cpu_class_init, }; +static const TypeInfo possible_cpus_interface_info = { + .name = TYPE_POSSIBLE_CPUS, + .parent = TYPE_INTERFACE, + .class_size = sizeof(PossibleCpusClass), +}; + static void cpu_register_types(void) { type_register_static(&cpu_type_info); + type_register_static(&possible_cpus_interface_info); } type_init(cpu_register_types)