From patchwork Wed Mar 30 08:49:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 8693841 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9BF899F36E for ; Wed, 30 Mar 2016 08:52:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD74B20279 for ; Wed, 30 Mar 2016 08:52:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0EBAD20155 for ; Wed, 30 Mar 2016 08:52:43 +0000 (UTC) Received: from localhost ([::1]:52539 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBrm-0006Ng-FJ for patchwork-qemu-devel@patchwork.kernel.org; Wed, 30 Mar 2016 04:52:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34192) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpp-0002oL-VW for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alBpo-0001ql-Qq for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:41 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:42861) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alBpo-0001qf-L0 for qemu-devel@nongnu.org; Wed, 30 Mar 2016 04:50:40 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 06F56873A288E for ; Wed, 30 Mar 2016 09:50:37 +0100 (IST) Received: from lalrae-linux.kl.imgtec.org (192.168.169.37) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 30 Mar 2016 09:50:39 +0100 From: Leon Alrae To: Date: Wed, 30 Mar 2016 09:49:55 +0100 Message-ID: <1459327802-5102-15-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> References: <1459327802-5102-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.169.37] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Empty/Full Synchronized and Try views can be used to access FIFO cells. Store to the FIFO cell pushes the value into the queue, load pops the oldest element from the queue. Cell's Full and Empty bits are automatically updated to reflect new state of the cell. Empty/Full Synchronized View causes the issuing thread to block when FIFO is empty while thread is performing a read, or FIFO is full while thread is performing a write. Empty/Full Try View never blocks the thread. If cell is full then write is ignored, if cell is empty then load returns 0. Trap bit (i.e. Gating Storage exceptions) not implemented. Store Conditional support for E/F Try View (i.e. indicate failure if FIFO is full) not implemented. Signed-off-by: Leon Alrae --- hw/misc/mips_itu.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 120b14c..24a1474 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -160,6 +160,26 @@ static inline ITCStorageCell *get_cell(MIPSITUState *s, return &s->cell[cell_idx]; } +static void wake_blocked_threads(ITCStorageCell *c) +{ + CPUState *cs; + CPU_FOREACH(cs) { + if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) { + cpu_interrupt(cs, CPU_INTERRUPT_WAKE); + } + } + c->blocked_threads = 0; +} + +static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c) +{ + c->blocked_threads |= 1ULL << current_cpu->cpu_index; + cpu_restore_state(current_cpu, current_cpu->mem_io_pc); + current_cpu->halted = 1; + current_cpu->exception_index = EXCP_HLT; + cpu_loop_exit(current_cpu); +} + /* ITC Control View */ static inline uint64_t view_control_read(ITCStorageCell *c) @@ -183,6 +203,87 @@ static inline void view_control_write(ITCStorageCell *c, uint64_t val) } } +/* ITC Empty/Full View */ + +static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking) +{ + uint64_t ret = 0; + + if (!c->tag.FIFO) { + return 0; + } + + c->tag.F = 0; + + if (blocking && c->tag.E) { + block_thread_and_exit(c); + } + + if (c->blocked_threads) { + wake_blocked_threads(c); + } + + if (c->tag.FIFOPtr > 0) { + ret = c->data[c->fifo_out]; + c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH; + c->tag.FIFOPtr--; + } + + if (c->tag.FIFOPtr == 0) { + c->tag.E = 1; + } + + return ret; +} + +static uint64_t view_ef_sync_read(ITCStorageCell *c) +{ + return view_ef_common_read(c, true); +} + +static uint64_t view_ef_try_read(ITCStorageCell *c) +{ + return view_ef_common_read(c, false); +} + +static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val, + bool blocking) +{ + if (!c->tag.FIFO) { + return; + } + + c->tag.E = 0; + + if (blocking && c->tag.F) { + block_thread_and_exit(c); + } + + if (c->blocked_threads) { + wake_blocked_threads(c); + } + + if (c->tag.FIFOPtr < ITC_CELL_DEPTH) { + int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH; + c->data[idx] = val; + c->tag.FIFOPtr++; + } + + if (c->tag.FIFOPtr == ITC_CELL_DEPTH) { + c->tag.F = 1; + } +} + +static void view_ef_sync_write(ITCStorageCell *c, uint64_t val) +{ + view_ef_common_write(c, val, true); +} + +static void view_ef_try_write(ITCStorageCell *c, uint64_t val) +{ + view_ef_common_write(c, val, false); +} + static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) { MIPSITUState *s = (MIPSITUState *)opaque; @@ -194,6 +295,12 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size) case ITCVIEW_CONTROL: ret = view_control_read(cell); break; + case ITCVIEW_EF_SYNC: + ret = view_ef_sync_read(cell); + break; + case ITCVIEW_EF_TRY: + ret = view_ef_try_read(cell); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_read: Bad ITC View %d\n", (int)view); @@ -214,6 +321,12 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data, case ITCVIEW_CONTROL: view_control_write(cell, data); break; + case ITCVIEW_EF_SYNC: + view_ef_sync_write(cell, data); + break; + case ITCVIEW_EF_TRY: + view_ef_try_write(cell, data); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "itc_storage_write: Bad ITC View %d\n", (int)view);