From patchwork Wed May 4 20:12:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9018661 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3F319BF29F for ; Wed, 4 May 2016 20:29:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3EAA02020F for ; Wed, 4 May 2016 20:29:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7AC43201EC for ; Wed, 4 May 2016 20:29:29 +0000 (UTC) Received: from localhost ([::1]:50142 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3QD-0006A2-LI for patchwork-qemu-devel@patchwork.kernel.org; Wed, 04 May 2016 16:29:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3DB-0004Mh-A7 for qemu-devel@nongnu.org; Wed, 04 May 2016 16:16:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay3Cy-0004XI-Ow for qemu-devel@nongnu.org; Wed, 04 May 2016 16:15:51 -0400 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:21525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay3Cy-0004PB-5j for qemu-devel@nongnu.org; Wed, 04 May 2016 16:15:44 -0400 Received: from Quad.localdomain (unknown [IPv6:2a01:e34:eeee:5240:12c3:7bff:fe6b:9a76]) by smtp1-g21.free.fr (Postfix) with ESMTPS id 42790B00525; Wed, 4 May 2016 20:09:06 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 22:12:06 +0200 Message-Id: <1462392752-17703-27-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1462392752-17703-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 2a01:e0c:1:1599::10 Subject: [Qemu-devel] [PATCH 26/52] target-m68k: Inline shifts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , rth@twiddle.net, schwab@linux-m68k.org, agraf@suse.de, gerg@uclinux.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Richard Henderson Signed-off-by: Richard Henderson fix arithmetical/logical switch Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target-m68k/helper.c | 52 --------------------------- target-m68k/helper.h | 3 -- target-m68k/translate.c | 94 +++++++++++++++++++++++++++++++++++++------------ 3 files changed, 72 insertions(+), 77 deletions(-) diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 8758016..0ca8d3f 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -323,58 +323,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val) m68k_switch_sp(env); } -uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t result; - - shift &= 63; - result = (uint64_t)val << shift; - - env->cc_c = (result >> 32) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (uint64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = 0; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - -uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift) -{ - uint64_t temp; - uint32_t result; - - shift &= 63; - temp = (int64_t)val << 32 >> shift; - result = temp >> 32; - - env->cc_c = (temp >> 31) & 1; - env->cc_n = result; - env->cc_z = result; - env->cc_v = result ^ val; - env->cc_x = shift ? env->cc_c : env->cc_x; - - return result; -} - /* FPU helpers. */ uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val) { diff --git a/target-m68k/helper.h b/target-m68k/helper.h index c868148..9985f9b 100644 --- a/target-m68k/helper.h +++ b/target-m68k/helper.h @@ -5,9 +5,6 @@ DEF_HELPER_2(divu, void, env, i32) DEF_HELPER_2(divs, void, env, i32) DEF_HELPER_3(addx_cc, i32, env, i32, i32) DEF_HELPER_3(subx_cc, i32, env, i32, i32) -DEF_HELPER_3(shl_cc, i32, env, i32, i32) -DEF_HELPER_3(shr_cc, i32, env, i32, i32) -DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(movec, void, env, i32, i32) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 58cc9d9..1e8cb37 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2038,48 +2038,98 @@ DISAS_INSN(addx) gen_helper_addx_cc(reg, cpu_env, reg, src); } -/* TODO: This could be implemented without helper functions. */ DISAS_INSN(shift_im) { - TCGv reg; - int tmp; - TCGv shift; + TCGv reg = DREG(insn, 0); + int count = (insn >> 9) & 7; + int logical = insn & 8; - set_cc_op(s, CC_OP_FLAGS); + if (count == 0) { + count = 8; + } - reg = DREG(insn, 0); - tmp = (insn >> 9) & 7; - if (tmp == 0) - tmp = 8; - shift = tcg_const_i32(tmp); - /* No need to flush flags becuse we know we will set C flag. */ if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count); + tcg_gen_shli_i32(QREG_CC_N, reg, count); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); + if (logical) { + tcg_gen_shri_i32(QREG_CC_N, reg, count); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sari_i32(QREG_CC_N, reg, count); } } + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); + + /* Note that ColdFire always clears V, while M68000 sets it for + a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } else { + tcg_gen_movi_i32(QREG_CC_V, 0); + } + + tcg_gen_mov_i32(reg, QREG_CC_N); + set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(shift_reg) { - TCGv reg; - TCGv shift; + TCGv reg, s32; + TCGv_i64 t64, s64; + int logical = insn & 8; reg = DREG(insn, 0); - shift = DREG(insn, 9); + t64 = tcg_temp_new_i64(); + s64 = tcg_temp_new_i64(); + s32 = tcg_temp_new(); + + /* Note that m68k truncates the shift count modulo 64, not 32. + In addition, a 64-bit shift makes it easy to find "the last + bit shifted out", for the carry flag. */ + tcg_gen_andi_i32(s32, DREG(insn, 9), 63); + tcg_gen_extu_i32_i64(s64, s32); + + /* Non-arithmetic shift clears V. Use it as a source zero here. */ + tcg_gen_movi_i32(QREG_CC_V, 0); + if (insn & 0x100) { - gen_helper_shl_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shl_i64(t64, t64, s64); + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); + tcg_temp_free_i64(t64); + tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); } else { - if (insn & 8) { - gen_helper_shr_cc(reg, cpu_env, reg, shift); + tcg_gen_extu_i32_i64(t64, reg); + tcg_gen_shli_i64(t64, t64, 32); + if (logical) { + tcg_gen_shr_i64(t64, t64, s64); } else { - gen_helper_sar_cc(reg, cpu_env, reg, shift); + tcg_gen_sar_i64(t64, t64, s64); } + tcg_temp_free_i64(s64); + tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64); + tcg_temp_free_i64(t64); + tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31); } + tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); + + /* Note that X = C, but only if the shift count was non-zero. */ + tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, + QREG_CC_C, QREG_CC_X); + tcg_temp_free(s32); + + /* Note that ColdFire always clears V (which we have done above), + while M68000 sets it for a change in the sign bit. */ + if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) { + tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg); + } + + /* Write back the result. */ + tcg_gen_mov_i32(reg, QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); }