From patchwork Wed May 4 21:08:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 9018801 Return-Path: X-Original-To: patchwork-qemu-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 88841BF29F for ; Wed, 4 May 2016 21:11:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9DDCB203B8 for ; Wed, 4 May 2016 21:11:18 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 839D5203B4 for ; Wed, 4 May 2016 21:11:17 +0000 (UTC) Received: from localhost ([::1]:50291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay44f-0000hw-KJ for patchwork-qemu-devel@patchwork.kernel.org; Wed, 04 May 2016 17:11:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay44E-00006G-2m for qemu-devel@nongnu.org; Wed, 04 May 2016 17:11:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ay441-0000Sk-Ha for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:40 -0400 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:17820) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ay441-0000La-00 for qemu-devel@nongnu.org; Wed, 04 May 2016 17:10:33 -0400 Received: from Quad.localdomain (unknown [IPv6:2a01:e34:eeee:5240:12c3:7bff:fe6b:9a76]) by smtp1-g21.free.fr (Postfix) with ESMTPS id B7519B0032C; Wed, 4 May 2016 21:03:54 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Wed, 4 May 2016 23:08:38 +0200 Message-Id: <1462396135-20925-3-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1462396135-20925-1-git-send-email-laurent@vivier.eu> References: <1462392752-17703-1-git-send-email-laurent@vivier.eu> <1462396135-20925-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 2a01:e0c:1:1599::10 Subject: [Qemu-devel] [PATCH 35/52] target-m68k: inline rotate ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , gerg@uclinux.org, schwab@linux-m68k.org, agraf@suse.de, rth@twiddle.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 353 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 353 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 1d05c6a..d183a3c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -2710,6 +2710,352 @@ DISAS_INSN(shift_reg) set_cc_op(s, CC_OP_FLAGS); } +static inline void rotate(TCGv reg, TCGv shift, int left, int size) +{ + if (size == 32) { + if (left) { + tcg_gen_rotl_i32(reg, reg, shift); + } else { + tcg_gen_rotr_i32(reg, reg, shift); + } + } else { + TCGv t0; + + if (left) { + tcg_gen_shl_i32(reg, reg, shift); + } else { + tcg_gen_shli_i32(reg, reg, size); + tcg_gen_shr_i32(reg, reg, shift); + } + + t0 = tcg_temp_new(); + tcg_gen_shri_i32(t0, reg, size); + tcg_gen_or_i32(reg, reg, t0); + tcg_temp_free(t0); + if (size == 8) { + tcg_gen_ext8s_i32(reg, reg); + } else if (size == 16) { + tcg_gen_ext16s_i32(reg, reg); + } + } + + if (left) { + tcg_gen_andi_i32(QREG_CC_C, reg, 1); + } else { + tcg_gen_shri_i32(QREG_CC_C, reg, 31); + } + + tcg_gen_movi_i32(QREG_CC_V, 0); + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); +} + +static inline void rotate_x_flags(TCGv reg, int size) +{ + switch (size) { + case 8: + tcg_gen_ext8s_i32(reg, reg); + break; + case 16: + tcg_gen_ext16s_i32(reg, reg); + break; + default: + break; + } + tcg_gen_mov_i32(QREG_CC_N, reg); + tcg_gen_mov_i32(QREG_CC_Z, reg); + tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); +} + +static inline void rotate_x(TCGv dest, TCGv X, TCGv reg, TCGv shift, + int left, int size) +{ + TCGv_i64 t0, shift64; + TCGv lo, hi; + + shift64 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(shift64, shift); + + t0 = tcg_temp_new_i64(); + + lo = tcg_temp_new(); + hi = tcg_temp_new(); + + if (left) { + /* create [reg:X:..] */ + + if (size == 32) { + tcg_gen_shli_i32(X, QREG_CC_X, 31); + tcg_gen_concat_i32_i64(t0, X, reg); + } else { + tcg_gen_shli_i32(X, reg, 1); + tcg_gen_or_i32(X, X, QREG_CC_X); + tcg_gen_extu_i32_i64(t0, X); + tcg_gen_shli_i64(t0, t0, 64 - size - 1); + } + + /* rotate */ + + tcg_gen_rotl_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is [reg:..:reg:X] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + tcg_gen_andi_i32(X, lo, 1); + + tcg_gen_shri_i32(lo, lo, 1); + tcg_gen_shri_i32(hi, hi, 32 - size); + tcg_gen_or_i32(dest, lo, hi); + } else { + if (size == 32) { + tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X); + } else { + tcg_gen_shli_i32(X, QREG_CC_X, size); + tcg_gen_or_i32(X, reg, X); + tcg_gen_extu_i32_i64(t0, X); + } + + tcg_gen_rotr_i64(t0, t0, shift64); + tcg_temp_free_i64(shift64); + + /* result is value: [X:reg:..:reg] */ + + tcg_gen_extr_i64_i32(lo, hi, t0); + + /* extract X */ + + tcg_gen_shri_i32(X, hi, 31); + + /* extract result */ + + tcg_gen_shli_i32(hi, hi, 1); + tcg_gen_shri_i32(hi, hi, 32 - size); + tcg_gen_or_i32(dest, lo, hi); + } + tcg_temp_free(hi); + tcg_temp_free(lo); + tcg_temp_free_i64(t0); + + tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */ +} + +DISAS_INSN(rotate_im) +{ + TCGv reg; + TCGv shift; + int tmp; + int left = (insn & 0x100); + + reg = DREG(insn, 0); + tmp = (insn >> 9) & 7; + tmp = ((tmp - 1) & 7) + 1; /* 1..8 */ + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 32); + } else { + rotate_x(reg, QREG_CC_X, reg, shift, left, 32); + rotate_x_flags(reg, 32); + } + tcg_temp_free(shift); + + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + + tmp = (insn >> 9) & 7; + tmp = ((tmp - 1) & 7) + 1; /* 1..8 */ + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 8); + } else { + rotate_x(reg, QREG_CC_X, reg, shift, left, 8); + rotate_x_flags(reg, 8); + } + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_im) +{ + int left = (insn & 0x100); + TCGv reg; + TCGv shift; + int tmp; + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + tmp = (insn >> 9) & 7; + tmp = ((tmp - 1) & 7) + 1; /* 1..8 */ + + shift = tcg_const_i32(tmp); + if (insn & 8) { + rotate(reg, shift, left, 16); + } else { + rotate_x(reg, QREG_CC_X, reg, shift, left, 16); + rotate_x_flags(reg, 8); + } + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_reg) +{ + TCGv reg; + TCGv src; + TCGv tmp, t0; + int left = (insn & 0x100); + + reg = DREG(insn, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(tmp, src, 31); + rotate(reg, tmp, left, 32); + /* if shift == 0, clear C */ + tcg_gen_andi_i32(tmp, src, 63); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + tmp, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv dest, X; + dest = tcg_temp_new(); + X = tcg_temp_new(); + /* shift in [0..63] */ + tcg_gen_andi_i32(tmp, src, 63); + /* modulo 33 */ + t0 = tcg_const_i32(33); + tcg_gen_remu_i32(tmp, tmp, t0); + tcg_temp_free(t0); + rotate_x(dest, X, reg, tmp, left, 32); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_X, + tmp, QREG_CC_V /* 0 */, + QREG_CC_X /* 0 */, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + tmp, QREG_CC_V /* 0 */, + reg /* 0 */, dest); + tcg_temp_free(X); + tcg_temp_free(dest); + rotate_x_flags(reg, 32); + } + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate8_reg) +{ + TCGv reg; + TCGv src; + TCGv tmp, t0; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_BYTE, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(tmp, src, 7); + rotate(reg, tmp, left, 8); + /* if shift == 0, clear C */ + tcg_gen_andi_i32(tmp, src, 63); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + tmp, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv dest, X; + dest = tcg_temp_new(); + X = tcg_temp_new(); + /* shift in [0..63] */ + tcg_gen_andi_i32(tmp, src, 63); + /* modulo 9 */ + t0 = tcg_const_i32(9); + tcg_gen_remu_i32(tmp, tmp, t0); + tcg_temp_free(t0); + rotate_x(dest, X, reg, tmp, left, 8); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_X, + tmp, QREG_CC_V /* 0 */, + QREG_CC_X /* 0 */, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + tmp, QREG_CC_V /* 0 */, + reg /* 0 */, dest); + tcg_temp_free(X); + tcg_temp_free(dest); + rotate_x_flags(reg, 8); + } + gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate16_reg) +{ + TCGv reg; + TCGv src; + TCGv tmp, t0; + int left = (insn & 0x100); + + reg = gen_extend(DREG(insn, 0), OS_WORD, 0); + src = DREG(insn, 9); + tmp = tcg_temp_new_i32(); + if (insn & 8) { + tcg_gen_andi_i32(tmp, src, 15); + rotate(reg, tmp, left, 16); + /* if shift == 0, clear C */ + tcg_gen_andi_i32(tmp, src, 63); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, + tmp, QREG_CC_V /* 0 */, + QREG_CC_V /* 0 */, QREG_CC_C); + } else { + TCGv dest, X; + dest = tcg_temp_new(); + X = tcg_temp_new(); + /* shift in [0..63] */ + tcg_gen_andi_i32(tmp, src, 63); + /* modulo 17 */ + t0 = tcg_const_i32(17); + tcg_gen_remu_i32(tmp, tmp, t0); + tcg_temp_free(t0); + rotate_x(dest, X, reg, tmp, left, 16); + tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_X, + tmp, QREG_CC_V /* 0 */, + QREG_CC_X /* 0 */, X); + tcg_gen_movcond_i32(TCG_COND_EQ, reg, + tmp, QREG_CC_V /* 0 */, + reg /* 0 */, dest); + tcg_temp_free(X); + tcg_temp_free(dest); + rotate_x_flags(reg, 16); + } + gen_partset_reg(OS_WORD, DREG(insn, 0), reg); + set_cc_op(s, CC_OP_FLAGS); +} + +DISAS_INSN(rotate_mem) +{ + TCGv src; + TCGv addr; + TCGv shift; + int left = (insn & 0x100); + + SRC_EA(env, src, OS_WORD, 0, &addr); + + shift = tcg_const_i32(1); + if (insn & 8) { + rotate(src, shift, left, 16); + } else { + rotate_x(src, QREG_CC_X, src, shift, left, 16); + rotate_x_flags(src, 16); + } + DEST_EA(env, insn, OS_WORD, src, &addr); + set_cc_op(s, CC_OP_FLAGS); +} + static void bitfield_param(uint16_t ext, TCGv *offset, TCGv *width, TCGv *mask) { TCGv tmp; @@ -4105,6 +4451,13 @@ void register_m68k_insns (CPUM68KState *env) INSN(adda, d0c0, f0c0, M68000); INSN(shift_im, e080, f0f0, CF_ISA_A); INSN(shift_reg, e0a0, f0f0, CF_ISA_A); + INSN(rotate_im, e090, f0f0, M68000); + INSN(rotate8_im, e010, f0f0, M68000); + INSN(rotate16_im, e050, f0f0, M68000); + INSN(rotate_reg, e0b0, f0f0, M68000); + INSN(rotate8_reg, e030, f0f0, M68000); + INSN(rotate16_reg,e070, f0f0, M68000); + INSN(rotate_mem, e4c0, fcc0, M68000); INSN(bitfield_mem,e8c0, f8c0, BITFIELD); INSN(bitfield_reg,e8c0, f8f8, BITFIELD); INSN(undef_fpu, f000, f000, CF_ISA_A);