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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id 131sm1496505wmu.17.2016.05.19.15.48.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 May 2016 15:48:58 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Fri, 20 May 2016 00:48:51 +0200 Message-Id: <1463698133-30880-4-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1463698133-30880-1-git-send-email-edgar.iglesias@gmail.com> References: <1463698133-30880-1-git-send-email-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v1 3/5] xlnx-zynqmp: Make the RPU subsystem optional X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, crosthwaite.peter@gmail.com, edgar.iglesiasl@xilinx.com, qemu-arm@nongnu.org, alistair.francis@xilinx.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: "Edgar E. Iglesias" The way we currently model the RPU subsystem is of quite limited use. In addition to that, it causes problems for KVM and for GDB debugging. Make the RPU optional by adding a has_rpu property and default to having it disabled. Signed-off-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 50 +++++++++++++++++++++++++++++++++++++------- include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 250ecc4..c180206 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -83,6 +83,40 @@ static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; } +static bool xlnx_zynqmp_get_has_rpu(Object *obj, Error **errp) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(obj); + + return s->has_rpu; +} + +static void xlnx_zynqmp_set_has_rpu(Object *obj, bool value, Error **errp) +{ + XlnxZynqMPState *s = XLNX_ZYNQMP(obj); + int i; + + if (s->has_rpu == value) { + /* Nothing to do. */ + return; + } + + /* We don't support clearing the flag. */ + if (s->has_rpu) { + error_setg(errp, "has_rpu is already set to %u", + s->has_rpu); + return; + } + + /* Create the Cortex R5s. */ + for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { + object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), + "cortex-r5-" TYPE_ARM_CPU); + object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), + &error_abort); + } + s->has_rpu = value; +} + static void xlnx_zynqmp_setup_rpu(XlnxZynqMPState *s, const char *boot_cpu, Error **errp) { @@ -118,6 +152,11 @@ static void xlnx_zynqmp_init(Object *obj) XlnxZynqMPState *s = XLNX_ZYNQMP(obj); int i; + object_property_add_bool(obj, "has_rpu", + xlnx_zynqmp_get_has_rpu, + xlnx_zynqmp_set_has_rpu, + &error_abort); + for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), "cortex-a53-" TYPE_ARM_CPU); @@ -125,13 +164,6 @@ static void xlnx_zynqmp_init(Object *obj) &error_abort); } - for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { - object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), - "cortex-r5-" TYPE_ARM_CPU); - object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), - &error_abort); - } - object_property_add_link(obj, "ddr-ram", TYPE_MEMORY_REGION, (Object **)&s->ddr_ram, qdev_prop_allow_set_link_before_realize, @@ -290,7 +322,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); } - xlnx_zynqmp_setup_rpu(s, boot_cpu, errp); + if (s->has_rpu) { + xlnx_zynqmp_setup_rpu(s, boot_cpu, errp); + } if (!s->boot_cpu_ptr) { error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 38d4c8c..68f6eb0 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -87,6 +87,8 @@ typedef struct XlnxZynqMPState { /* Has the ARM Security extensions? */ bool secure; + /* Has the RPU subsystem? */ + bool has_rpu; } XlnxZynqMPState; #define XLNX_ZYNQMP_H