From patchwork Mon Jun 13 15:50:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?S09OUkFEIEZyw6lkw6lyaWM=?= X-Patchwork-Id: 9173531 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 57DCE6044F for ; Mon, 13 Jun 2016 15:58:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46F671FFC7 for ; Mon, 13 Jun 2016 15:58:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BA3725EF7; Mon, 13 Jun 2016 15:58:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, FSL_HELO_HOME, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7AB921FFC7 for ; Mon, 13 Jun 2016 15:58:21 +0000 (UTC) Received: from localhost ([::1]:57354 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCUFn-0002V4-Ii for patchwork-qemu-devel@patchwork.kernel.org; Mon, 13 Jun 2016 11:58:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCU8L-00044x-SF for qemu-devel@nongnu.org; Mon, 13 Jun 2016 11:50:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCU8H-0008Q6-IK for qemu-devel@nongnu.org; Mon, 13 Jun 2016 11:50:37 -0400 Received: from greensocs.com ([193.104.36.180]:55162) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCU8H-0008Pl-18 for qemu-devel@nongnu.org; Mon, 13 Jun 2016 11:50:33 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 5C35FBBFC26; Mon, 13 Jun 2016 17:50:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1465833032; bh=8QCzMxTJpRdS7CbCl+MKqZonF9FfCu5O6Xh7fDpy1yc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=M3Q8eVB9rP598yclxcQWQU2PVvFuydcNzbAkyxDGZV+K2nXOJ4LIm6fBdmk5M+Di0 b/7ngf1t6qClAi7dra5EvM/WW+z1OqDHcJM4X6K5tRVJQTzZTJthrvAAGSK3cppKaC UThtE3GXd1LiV+MBJcrtzLw+c/InTJX6WnwdK9Js= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8f8186L6XwK3; Mon, 13 Jun 2016 17:50:31 +0200 (CEST) Received: from corsair.home (AToulouse-659-1-111-162.w90-38.abo.wanadoo.fr [90.38.166.162]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: fred.konrad@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id A7AD013897B9; Mon, 13 Jun 2016 17:50:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1465833029; bh=8QCzMxTJpRdS7CbCl+MKqZonF9FfCu5O6Xh7fDpy1yc=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fXtdOVU+5At/st9GVMdb3CtPKBFCN5jHS3mbXX7yEfZa35KfZOf/Mym59tQRea8yN eO4C0tPCr6o4L857OtDEruY2bGEFnxbCYg/X2Fn0Qkw8eUpcPwpP6blVEihEkwejvn yOce+IhHN5CudL2sOA+GDaOtqtSFY9LNuXKCl4z8= From: fred.konrad@greensocs.com To: qemu-devel@nongnu.org Date: Mon, 13 Jun 2016 17:50:10 +0200 Message-Id: <1465833014-21982-6-git-send-email-fred.konrad@greensocs.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1465833014-21982-1-git-send-email-fred.konrad@greensocs.com> References: <1465833014-21982-1-git-send-email-fred.konrad@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH V10 5/9] introduce dpcd module X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, hyunk@xilinx.com, mark.burton@greensocs.com, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, guillaume.delbergue@greensocs.com, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: KONRAD Frederic This introduces dpcd module. It wires on a aux-bus and can be accessed by the driver to get lane-speed, etc. Signed-off-by: KONRAD Frederic Reviewed-by: Alistair Francis Reviewed-by: Peter Crosthwaite Tested-By: Hyun Kwon --- default-configs/aarch64-softmmu.mak | 1 + hw/display/Makefile.objs | 1 + hw/display/dpcd.c | 173 ++++++++++++++++++++++++++++++++++++ include/hw/display/dpcd.h | 105 ++++++++++++++++++++++ 4 files changed, 280 insertions(+) create mode 100644 hw/display/dpcd.c create mode 100644 include/hw/display/dpcd.h diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak index d3a2665..87165b7 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -4,4 +4,5 @@ include arm-softmmu.mak CONFIG_AUX=y +CONFIG_DPCD=y CONFIG_XLNX_ZYNQMP=y diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index d99780e..ddf3275 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -43,3 +43,4 @@ virtio-gpu.o-cflags := $(VIRGL_CFLAGS) virtio-gpu.o-libs += $(VIRGL_LIBS) virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS) virtio-gpu-3d.o-libs += $(VIRGL_LIBS) +obj-$(CONFIG_DPCD) += dpcd.o diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c new file mode 100644 index 0000000..5a36855 --- /dev/null +++ b/hw/display/dpcd.c @@ -0,0 +1,173 @@ +/* + * dpcd.c + * + * Copyright (C) 2015 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +/* + * This is a simple AUX slave which emulates a connected screen. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/aux.h" +#include "hw/display/dpcd.h" + +#ifndef DEBUG_DPCD +#define DEBUG_DPCD 0 +#endif + +#define DPRINTF(fmt, ...) do { \ + if (DEBUG_DPCD) { \ + qemu_log("dpcd: " fmt, ## __VA_ARGS__); \ + } \ +} while (0); + +#define DPCD_READABLE_AREA 0x600 + +struct DPCDState { + /*< private >*/ + AUXSlave parent_obj; + + /*< public >*/ + /* + * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF. + */ + uint8_t dpcd_info[DPCD_READABLE_AREA]; + + MemoryRegion iomem; +}; + +static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size) +{ + uint8_t ret; + DPCDState *e = DPCD(opaque); + + if (offset < DPCD_READABLE_AREA) { + ret = e->dpcd_info[offset]; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", + offset); + ret = 0; + } + + DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset); + return ret; +} + +static void dpcd_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + DPCDState *e = DPCD(opaque); + + DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset); + + if (offset < DPCD_READABLE_AREA) { + e->dpcd_info[offset] = value; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", + offset); + } +} + +static const MemoryRegionOps aux_ops = { + .read = dpcd_read, + .write = dpcd_write, + .valid = { + .min_access_size = 1, + .max_access_size = 1, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static void dpcd_reset(DeviceState *dev) +{ + DPCDState *s = DPCD(dev); + + memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info)); + + s->dpcd_info[DPCD_REVISION] = DPCD_REV_1_0; + s->dpcd_info[DPCD_MAX_LINK_RATE] = DPCD_5_4GBPS; + s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES; + s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_0] = DPCD_EDID_PRESENT; + /* buffer size */ + s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF; + + s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE + | DPCD_LANE0_CHANNEL_EQ_DONE + | DPCD_LANE0_SYMBOL_LOCKED + | DPCD_LANE1_CR_DONE + | DPCD_LANE1_CHANNEL_EQ_DONE + | DPCD_LANE1_SYMBOL_LOCKED; + s->dpcd_info[DPCD_LANE2_3_STATUS] = DPCD_LANE2_CR_DONE + | DPCD_LANE2_CHANNEL_EQ_DONE + | DPCD_LANE2_SYMBOL_LOCKED + | DPCD_LANE3_CR_DONE + | DPCD_LANE3_CHANNEL_EQ_DONE + | DPCD_LANE3_SYMBOL_LOCKED; + + s->dpcd_info[DPCD_LANE_ALIGN_STATUS_UPDATED] = DPCD_INTERLANE_ALIGN_DONE; + s->dpcd_info[DPCD_SINK_STATUS] = DPCD_RECEIVE_PORT_0_STATUS; +} + +static void dpcd_init(Object *obj) +{ + DPCDState *s = DPCD(obj); + + memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF); + aux_init_mmio(AUX_SLAVE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_dpcd = { + .name = TYPE_DPCD, + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0), + VMSTATE_END_OF_LIST() + } +}; + +static void dpcd_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->reset = dpcd_reset; + dc->vmsd = &vmstate_dpcd; +} + +static const TypeInfo dpcd_info = { + .name = TYPE_DPCD, + .parent = TYPE_AUX_SLAVE, + .instance_size = sizeof(DPCDState), + .class_init = dpcd_class_init, + .instance_init = dpcd_init, +}; + +static void dpcd_register_types(void) +{ + type_register_static(&dpcd_info); +} + +type_init(dpcd_register_types) diff --git a/include/hw/display/dpcd.h b/include/hw/display/dpcd.h new file mode 100644 index 0000000..274dc2e --- /dev/null +++ b/include/hw/display/dpcd.h @@ -0,0 +1,105 @@ +/* + * dpcd.h + * + * Copyright (C)2015 : GreenSocs Ltd + * http://www.greensocs.com/ , email: info@greensocs.com + * + * Developed by : + * Frederic Konrad + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + * + */ + +#ifndef DPCD_H +#define DPCD_H + +typedef struct DPCDState DPCDState; + +#define TYPE_DPCD "dpcd" +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD) + +/* DCPD Revision. */ +#define DPCD_REVISION 0x00 +#define DPCD_REV_1_0 0x10 +#define DPCD_REV_1_1 0x11 + +/* DCPD Max Link Rate. */ +#define DPCD_MAX_LINK_RATE 0x01 +#define DPCD_1_62GBPS 0x06 +#define DPCD_2_7GBPS 0x0A +#define DPCD_5_4GBPS 0x14 + +#define DPCD_MAX_LANE_COUNT 0x02 +#define DPCD_ONE_LANE 0x01 +#define DPCD_TWO_LANES 0x02 +#define DPCD_FOUR_LANES 0x04 + +/* DCPD Max down spread. */ +#define DPCD_UP_TO_0_5 0x01 +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40 + +/* DCPD Downstream port type. */ +#define DPCD_DISPLAY_PORT 0x00 +#define DPCD_ANALOG 0x02 +#define DPCD_DVI_HDMI 0x04 +#define DPCD_OTHER 0x06 + +/* DPCD Format conversion. */ +#define DPCD_FORMAT_CONVERSION 0x08 + +/* Main link channel coding. */ +#define DPCD_ANSI_8B_10B 0x01 + +/* Down stream port count. */ +#define DPCD_OUI_SUPPORTED 0x80 + +/* Receiver port capability. */ +#define DPCD_RECEIVE_PORT0_CAP_0 0x08 +#define DPCD_RECEIVE_PORT0_CAP_1 0x09 +#define DPCD_EDID_PRESENT 0x02 +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04 + +/* Down stream port capability. */ +#define DPCD_CAP_DISPLAY_PORT 0x000 +#define DPCD_CAP_ANALOG_VGA 0x001 +#define DPCD_CAP_DVI 0x002 +#define DPCD_CAP_HDMI 0x003 +#define DPCD_CAP_OTHER 0x100 + +#define DPCD_LANE0_1_STATUS 0x202 +#define DPCD_LANE0_CR_DONE (1 << 0) +#define DPCD_LANE0_CHANNEL_EQ_DONE (1 << 1) +#define DPCD_LANE0_SYMBOL_LOCKED (1 << 2) +#define DPCD_LANE1_CR_DONE (1 << 4) +#define DPCD_LANE1_CHANNEL_EQ_DONE (1 << 5) +#define DPCD_LANE1_SYMBOL_LOCKED (1 << 6) + +#define DPCD_LANE2_3_STATUS 0x203 +#define DPCD_LANE2_CR_DONE (1 << 0) +#define DPCD_LANE2_CHANNEL_EQ_DONE (1 << 1) +#define DPCD_LANE2_SYMBOL_LOCKED (1 << 2) +#define DPCD_LANE3_CR_DONE (1 << 4) +#define DPCD_LANE3_CHANNEL_EQ_DONE (1 << 5) +#define DPCD_LANE3_SYMBOL_LOCKED (1 << 6) + +#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DPCD_INTERLANE_ALIGN_DONE 0x01 +#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 +#define DPCD_LINK_STATUS_UPDATED 0x80 + +#define DPCD_SINK_STATUS 0x205 +#define DPCD_RECEIVE_PORT_0_STATUS 0x01 + +#endif /* !DPCD_H */