From patchwork Sun Jun 26 13:38:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 9199489 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5725060752 for ; Sun, 26 Jun 2016 13:39:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4991D2853F for ; Sun, 26 Jun 2016 13:39:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D8FB28543; Sun, 26 Jun 2016 13:39:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8E2112853F for ; Sun, 26 Jun 2016 13:39:54 +0000 (UTC) Received: from localhost ([::1]:54017 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHAHx-0001Qu-NZ for patchwork-qemu-devel@patchwork.kernel.org; Sun, 26 Jun 2016 09:39:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59904) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHAHS-0001Pm-Kc for qemu-devel@nongnu.org; Sun, 26 Jun 2016 09:39:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHAHP-00037q-On for qemu-devel@nongnu.org; Sun, 26 Jun 2016 09:39:22 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:38044) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHAHP-00037m-IK for qemu-devel@nongnu.org; Sun, 26 Jun 2016 09:39:19 -0400 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id EF10BBB90D8B for ; Sun, 26 Jun 2016 14:39:14 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Sun, 26 Jun 2016 14:39:18 +0100 From: Leon Alrae To: Date: Sun, 26 Jun 2016 14:38:35 +0100 Message-ID: <1466948322-27138-4-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466948322-27138-1-git-send-email-leon.alrae@imgtec.com> References: <1466948322-27138-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Markovic Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Aleksandar Markovic Only for Mips platform, and only for cases when snan_bit_is_one is 0, correct default NaN values (in their 16-, 32-, and 64-bit flavors). For more info, see [1], page 84, Table 6.3 "Value Supplied When a New Quiet NaN Is Created", and [2], page 52, Table 3.7 "Default NaN Encodings". [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 [2] "MIPS Architecture for Programmers Volume IV-j: The MIPS32 SIMD Architecture Module", Imagination Technologies LTD, Revision 1.12, February 3, 2016 Signed-off-by: Aleksandar Markovic Reviewed-by: Leon Alrae Reviewed-by: Peter Maydell Signed-off-by: Leon Alrae --- fpu/softfloat-specialize.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 981d665..a1bcb46 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -97,7 +97,11 @@ float16 float16_default_nan(float_status *status) if (status->snan_bit_is_one) { return const_float16(0x7DFF); } else { +#if defined(TARGET_MIPS) + return const_float16(0x7E00); +#else return const_float16(0xFE00); +#endif } #endif } @@ -116,7 +120,11 @@ float32 float32_default_nan(float_status *status) if (status->snan_bit_is_one) { return const_float32(0x7FBFFFFF); } else { +#if defined(TARGET_MIPS) + return const_float32(0x7FC00000); +#else return const_float32(0xFFC00000); +#endif } #endif } @@ -135,7 +143,11 @@ float64 float64_default_nan(float_status *status) if (status->snan_bit_is_one) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { +#if defined(TARGET_MIPS) + return const_float64(LIT64(0x7FF8000000000000)); +#else return const_float64(LIT64(0xFFF8000000000000)); +#endif } #endif }