From patchwork Mon Sep 19 06:29:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nikunj A. Dadhania" X-Patchwork-Id: 9338621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9AA4F607D0 for ; Mon, 19 Sep 2016 06:38:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E5C82684F for ; Mon, 19 Sep 2016 06:38:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 71F4C28599; Mon, 19 Sep 2016 06:38:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6E7C82684F for ; Mon, 19 Sep 2016 06:38:57 +0000 (UTC) Received: from localhost ([::1]:53119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1blsEC-0001W8-Mp for patchwork-qemu-devel@patchwork.kernel.org; Mon, 19 Sep 2016 02:38:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bls5f-00037I-Ty for qemu-devel@nongnu.org; Mon, 19 Sep 2016 02:30:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bls5X-00089V-Um for qemu-devel@nongnu.org; Mon, 19 Sep 2016 02:30:06 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:51627 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bls5X-00089D-OO for qemu-devel@nongnu.org; Mon, 19 Sep 2016 02:29:59 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8J6ShLH001514 for ; Mon, 19 Sep 2016 02:29:59 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0a-001b2d01.pphosted.com with ESMTP id 25h1u719p2-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 19 Sep 2016 02:29:59 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 19 Sep 2016 16:29:53 +1000 Received: from d23relay07.au.ibm.com (d23relay07.au.ibm.com [9.190.26.37]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id B73542CE8046; Mon, 19 Sep 2016 16:29:52 +1000 (EST) Received: from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u8J6TqnM6357476; Mon, 19 Sep 2016 16:29:52 +1000 Received: from d23av05.au.ibm.com (localhost [127.0.0.1]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u8J6TqVs012702; Mon, 19 Sep 2016 16:29:52 +1000 Received: from abhimanyu.in.ibm.com (abhimanyu.in.ibm.com [9.124.35.169]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u8J6TcTf012399; Mon, 19 Sep 2016 16:29:50 +1000 From: Nikunj A Dadhania To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Date: Mon, 19 Sep 2016 11:59:35 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474266577-11704-1-git-send-email-nikunj@linux.vnet.ibm.com> References: <1474266577-11704-1-git-send-email-nikunj@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16091906-0048-0000-0000-000001BEE9C4 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16091906-0049-0000-0000-0000469487FE Message-Id: <1474266577-11704-8-git-send-email-nikunj@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-19_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609190094 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [PATCH v4 7/9] ppc/xics: Add "native" XICS subclass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com, clg@kaod.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Benjamin Herrenschmidt This provides MMIO based ICP access as found on POWER8 Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Nikunj A Dadhania --- default-configs/ppc64-softmmu.mak | 3 +- hw/intc/Makefile.objs | 1 + hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++++++++ include/hw/ppc/xics.h | 14 ++ 4 files changed, 312 insertions(+), 1 deletion(-) create mode 100644 hw/intc/xics_native.c diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak index c4be59f..315e30b 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=y CONFIG_ETSEC=y CONFIG_LIBDECNUMBER=y # For pSeries -CONFIG_XICS=$(CONFIG_PSERIES) +CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV)) CONFIG_XICS_SPAPR=$(CONFIG_PSERIES) +CONFIG_XICS_NATIVE=$(CONFIG_POWERNV) CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) # For PReP CONFIG_MC146818RTC=y diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 05ec21b..7be5dfc 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o obj-$(CONFIG_SH4) += sh_intc.o obj-$(CONFIG_XICS) += xics.o obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o +obj-$(CONFIG_XICS_NATIVE) += xics_native.o obj-$(CONFIG_XICS_KVM) += xics_kvm.o obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o obj-$(CONFIG_S390_FLIC) += s390_flic.o diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c new file mode 100644 index 0000000..26e45cc --- /dev/null +++ b/hw/intc/xics_native.c @@ -0,0 +1,295 @@ +/* + * QEMU PowerPC hardware System Emulator + * + * Native version of ICS/ICP + * + * Copyright (c) 2010,2011 David Gibson, IBM Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "qemu/osdep.h" +#include "hw/hw.h" +#include "trace.h" +#include "qemu/timer.h" +#include "hw/ppc/xics.h" +#include "qapi/visitor.h" +#include "qapi/error.h" + +#include + +/* #define DEBUG_MM(fmt...) printf(fmt) */ +#define DEBUG_MM(fmt...) do { } while (0) + +static void xics_native_initfn(Object *obj) +{ + XICSState *xics = XICS_NATIVE(obj); + + QLIST_INIT(&xics->ics); +} + +static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width) +{ + XICSState *s = opaque; + int32_t cpu_id, server; + uint32_t val; + ICPState *ss; + bool byte0 = (width == 1 && (addr & 0x3) == 0); + + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12; + server = get_cpu_index_by_dt_id(cpu_id); + if (server < 0) { + fprintf(stderr, "XICS: Bad ICP server %d\n", server); + goto bad_access; + } + ss = &s->ss[server]; + + switch (addr & 0xffc) { + case 0: /* poll */ + val = icp_ipoll(ss, NULL); + if (byte0) { + val >>= 24; + } else if (width != 4) { + goto bad_access; + } + break; + case 4: /* xirr */ + if (byte0) { + val = icp_ipoll(ss, NULL) >> 24; + } else if (width == 4) { + val = icp_accept(ss); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + val = ss->mfrr; + } else { + goto bad_access; + } + break; + case 16: + if (width == 4) { + val = ss->links[0]; + } else { + goto bad_access; + } + break; + case 20: + if (width == 4) { + val = ss->links[1]; + } else { + goto bad_access; + } + break; + case 24: + if (width == 4) { + val = ss->links[2]; + } else { + goto bad_access; + } + break; + default: +bad_access: + fprintf(stderr, "XICS: Bad ICP access %llx/%d\n", + (unsigned long long)addr, width); + val = 0xffffffff; + } + DEBUG_MM("icp_mm_read(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n", + (unsigned long long)addr, cpu_id, server, (int)(addr & 0xffc), + width, val); + + return val; +} + +static void icp_mm_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + XICSState *s = opaque; + int32_t cpu_id, server; + ICPState *ss; + bool byte0 = (width == 1 && (addr & 0x3) == 0); + + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12; + server = get_cpu_index_by_dt_id(cpu_id); + if (server < 0) { + fprintf(stderr, "XICS: Bad ICP server %d\n", server); + goto bad_access; + } + ss = &s->ss[server]; + + DEBUG_MM("icp_mm_write(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n", + (unsigned long long)addr, cpu_id, server, + (int)(addr & 0xffc), width, (uint32_t)val); + + switch (addr & 0xffc) { + case 4: /* xirr */ + if (byte0) { + icp_set_cppr(s, server, val); + } else if (width == 4) { + icp_eoi(s, server, val); + } else { + goto bad_access; + } + break; + case 12: + if (byte0) { + icp_set_mfrr(s, server, val); + } else { + goto bad_access; + } + break; + case 16: + if (width == 4) { + ss->links[0] = val; + } else { + goto bad_access; + } + break; + case 20: + if (width == 4) { + ss->links[1] = val; + } else { + goto bad_access; + } + break; + case 24: + if (width == 4) { + ss->links[2] = val; + } else { + goto bad_access; + } + break; + default: + bad_access: + val = 0xffffffff; + } +} + +static const MemoryRegionOps icp_mm_ops = { + .read = icp_mm_read, + .write = icp_mm_write, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, +}; + +#define _FDT(exp) \ + do { \ + int ret = (exp); \ + if (ret < 0) { \ + fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ + #exp, fdt_strerror(ret)); \ + exit(1); \ + } \ + } while (0) + +void xics_create_native_icp_node(XICSState *s, void *fdt, + uint32_t base, uint32_t count) +{ + uint64_t addr; + char *name; + const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; + uint32_t irange[2], i, rsize; + uint64_t *reg; + + addr = ICP_MM_BASE | (base << 12); + + irange[0] = cpu_to_be32(base); + irange[1] = cpu_to_be32(count); + + rsize = sizeof(uint64_t) * 2 * count; + reg = g_malloc(rsize); + for (i = 0; i < count; i++) { + reg[i * 2] = cpu_to_be64(addr | ((base + i) * 0x1000)); + reg[i * 2 + 1] = cpu_to_be64(0x1000); + } + + name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); + + /* interrupt controller */ + _FDT((fdt_begin_node(fdt, name))); + g_free(name); + + _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat)))); + _FDT((fdt_property(fdt, "reg", reg, rsize))); + _FDT((fdt_property_string(fdt, "device_type", + "PowerPC-External-Interrupt-Presentation"))); + _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); + _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", + irange, sizeof(irange)))); + _FDT((fdt_property_cell(fdt, "#interrupt-cells", 1))); + _FDT((fdt_property_cell(fdt, "#address-cells", 0))); + _FDT((fdt_end_node(fdt))); +} + +static void xics_native_realize(DeviceState *dev, Error **errp) +{ + XICSState *s = XICS_NATIVE(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *error = NULL; + int i; + + if (!s->nr_servers) { + error_setg(errp, "Number of servers needs to be greater 0"); + return; + } + + /* Register MMIO regions */ + memory_region_init_io(&s->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp", + ICP_MM_SIZE); + sysbus_init_mmio(sbd, &s->icp_mmio); + sysbus_mmio_map(sbd, 0, ICP_MM_BASE); + + for (i = 0; i < s->nr_servers; i++) { + object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &error); + if (error) { + error_propagate(errp, error); + return; + } + } +} + +static void xics_native_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + XICSStateClass *xsc = XICS_NATIVE_CLASS(oc); + + dc->realize = xics_native_realize; + xsc->set_nr_servers = xics_set_nr_servers; +} + +static const TypeInfo xics_native_info = { + .name = TYPE_XICS_NATIVE, + .parent = TYPE_XICS_COMMON, + .instance_size = sizeof(XICSState), + .class_size = sizeof(XICSStateClass), + .class_init = xics_native_class_init, + .instance_init = xics_native_initfn, +}; + +static void xics_native_register_types(void) +{ + type_register_static(&xics_native_info); +} +type_init(xics_native_register_types) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 2231f2a..f81155c 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -44,6 +44,9 @@ #define XICS_SPAPR_KVM(obj) \ OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM) +#define TYPE_XICS_NATIVE "xics-native" +#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE) + #define XICS_COMMON_CLASS(klass) \ OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) #define XICS_SPAPR_CLASS(klass) \ @@ -52,6 +55,8 @@ OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON) #define XICS_SPAPR_GET_CLASS(obj) \ OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR) +#define XICS_NATIVE_CLASS(klass) \ + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_NATIVE) #define XICS_IPI 0x2 #define XICS_BUID 0x1 @@ -86,6 +91,7 @@ struct XICSState { uint32_t nr_irqs; ICPState *ss; QLIST_HEAD(, ICSState) ics; + MemoryRegion icp_mmio; }; #define TYPE_ICP "icp" @@ -117,8 +123,13 @@ struct ICPState { uint8_t mfrr; qemu_irq output; bool cap_irq_xics_enabled; + uint32_t links[3]; }; +/* This should be an XSCOM BAR ... the size is arbitrary as well */ +#define ICP_MM_BASE 0x0003FFFF80000000 +#define ICP_MM_SIZE 0x0000000010000000 + #define TYPE_ICS_BASE "ics-base" #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) @@ -189,6 +200,9 @@ void xics_spapr_free(XICSState *icp, int irq, int num); void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu); +void xics_create_native_icp_node(XICSState *s, void *fdt, + uint32_t base, uint32_t count); + /* Internal XICS interfaces */ int xics_get_cpu_index_by_dt_id(int cpu_dt_id);