[v5,3/9] target-ppc: Implement mtvsrws instruction

Commit Message

Nikunj A. Dadhania Sept. 28, 2016, 6:41 p.m. UTC

From: Ravi Bangoria <[e-mail]>

mtvsrws: Move To VSR Word & Splat

Signed-off-by: Ravi Bangoria <[e-mail]>
Signed-off-by: Nikunj A Dadhania <[e-mail]>
Reviewed-by: Richard Henderson <[e-mail]>
---
 target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
 target-ppc/translate/vsx-ops.inc.c  |  1 +
 2 files changed, 24 insertions(+)

Comments

Richard Henderson Sept. 28, 2016, 8:21 p.m. UTC | #1

On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
> +    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);

Why are you using t0?


r~

David Gibson Sept. 29, 2016, 1:53 a.m. UTC | #2

On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote:
> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
> > +    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> > +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
> 
> Why are you using t0?

Richard, I don't quite understand your question.  This looks correct
to me.  It's duplicating the low 32-bits of rA into both the low-and
high 32-bits of t0, which will then be store to both the low and high
64-bit elements of the VSR.  That matches the instruction definition
which puts the low 32-bits of RA into every 32-bit element of the
vector.

Nikunj A. Dadhania Sept. 29, 2016, 2:19 a.m. UTC | #3

Richard Henderson <[e-mail]> writes:

> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
>> +    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
>> +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
>
> Why are you using t0?

Thought about dropping it, but wasn't sure if deposit_i64 would change it.

Regards,
Nikunj

Richard Henderson Sept. 29, 2016, 4:07 a.m. UTC | #4

On 09/28/2016 06:53 PM, David Gibson wrote:
> On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote:
>> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
>>> +    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
>>> +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
>>
>> Why are you using t0?
>
> Richard, I don't quite understand your question.

There's no need for the copy into t0 -- just put rA into those two arguments.


r~

Richard Henderson Sept. 29, 2016, 4:08 a.m. UTC | #5

On 09/28/2016 07:19 PM, Nikunj A Dadhania wrote:
> Richard Henderson <[e-mail]> writes:
>
>> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
>>> +    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
>>> +    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
>>
>> Why are you using t0?
>
> Thought about dropping it, but wasn't sure if deposit_i64 would change it.

Nope, all of the tcg-op.c functions are safe that way, only modifying the outputs.


r~

Patch

diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index c4c50dd..fa8240f 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -257,6 +257,29 @@  static void gen_mtvsrdd(DisasContext *ctx)
     tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);
 }
 
+static void gen_mtvsrws(DisasContext *ctx)
+{
+    TCGv_i64 t0 = tcg_temp_new_i64();
+
+    if (xT(ctx->opcode) < 32) {
+        if (unlikely(!ctx->vsx_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VSXU);
+            return;
+        }
+    } else {
+        if (unlikely(!ctx->altivec_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VPU);
+            return;
+        }
+    }
+
+    tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
+    tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xT(ctx->opcode)));
+
+    tcg_temp_free_i64(t0);
+}
+
 #endif
 
 static void gen_xxpermdi(DisasContext *ctx)
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 1287973..d5f5b87 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -24,6 +24,7 @@  GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mtvsrws, 0x1F, 0x13, 0x0C, 0x0000F800, PPC_NONE, PPC2_ISA300),
 #endif
 
 #define GEN_XX1FORM(name, opc2, opc3, fl2)                              \