From patchwork Wed Nov 2 22:22:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 9409983 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0007560722 for ; Wed, 2 Nov 2016 22:25:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E50952A5E9 for ; Wed, 2 Nov 2016 22:25:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D9C3A2A5E2; Wed, 2 Nov 2016 22:25:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4F85E2A5E0 for ; Wed, 2 Nov 2016 22:25:31 +0000 (UTC) Received: from localhost ([::1]:58022 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c23yL-0004wy-Pv for patchwork-qemu-devel@patchwork.kernel.org; Wed, 02 Nov 2016 18:25:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c23vN-00036i-SR for qemu-devel@nongnu.org; Wed, 02 Nov 2016 18:22:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c23vM-0007ph-Hb for qemu-devel@nongnu.org; Wed, 02 Nov 2016 18:22:25 -0400 Received: from mx1.redhat.com ([209.132.183.28]:51842) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c23vM-0007pB-9Q for qemu-devel@nongnu.org; Wed, 02 Nov 2016 18:22:24 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 89BAE8CB56; Wed, 2 Nov 2016 22:22:23 +0000 (UTC) Received: from weilaptop.redhat.com (unused [10.10.50.104] (may be forged)) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uA2MMHAR001149; Wed, 2 Nov 2016 18:22:22 -0400 From: Wei Huang To: cov@codeaurora.org Date: Wed, 2 Nov 2016 17:22:17 -0500 Message-Id: <1478125337-11770-4-git-send-email-wei@redhat.com> In-Reply-To: <1478125337-11770-1-git-send-email-wei@redhat.com> References: <1478125337-11770-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Wed, 02 Nov 2016 22:22:23 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCHv7 3/3] arm: pmu: Add CPI checking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alindsay@codeaurora.org, drjones@redhat.com, kvm@vger.kernel.org, croberts@codeaurora.org, qemu-devel@nongnu.org, alistair.francis@xilinx.com, shannon.zhao@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Calculate the numbers of cycles per instruction (CPI) implied by ARM PMU cycle counter values. Signed-off-by: Christopher Covington --- arm/pmu.c | 109 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 108 insertions(+), 1 deletion(-) diff --git a/arm/pmu.c b/arm/pmu.c index 65b7df1..ca00422 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -62,6 +62,23 @@ static inline void disable_counter(uint32_t idx) { asm volatile("mrc p15, 0, %0, c9, c12, 1" : : "r" (1 << idx)); } + +/* + * Extra instructions inserted by the compiler would be difficult to compensate + * for, so hand assemble everything between, and including, the PMCR accesses + * to start and stop counting. + */ +static inline void loop(int i, uint32_t pmcr) +{ + asm volatile( + " mcr p15, 0, %[pmcr], c9, c12, 0\n" + "1: subs %[i], %[i], #1\n" + " bgt 1b\n" + " mcr p15, 0, %[z], c9, c12, 0\n" + : [i] "+r" (i) + : [pmcr] "r" (pmcr), [z] "r" (0) + : "cc"); +} #elif defined(__aarch64__) static inline uint32_t get_pmcr(void) { @@ -98,6 +115,23 @@ static inline void disable_counter(uint32_t idx) { asm volatile("msr pmcntensclr_el0, %0" : : "r" (1 << idx)); } + +/* + * Extra instructions inserted by the compiler would be difficult to compensate + * for, so hand assemble everything between, and including, the PMCR accesses + * to start and stop counting. + */ +static inline void loop(int i, uint32_t pmcr) +{ + asm volatile( + " msr pmcr_el0, %[pmcr]\n" + "1: subs %[i], %[i], #1\n" + " b.gt 1b\n" + " msr pmcr_el0, xzr\n" + : [i] "+r" (i) + : [pmcr] "r" (pmcr) + : "cc"); +} #endif struct pmu_data { @@ -171,12 +205,85 @@ static bool check_cycles_increase(void) return true; } -int main(void) +/* + * Execute a known number of guest instructions. Only odd instruction counts + * greater than or equal to 3 are supported by the in-line assembly code. The + * control register (PMCR_EL0) is initialized with the provided value (allowing + * for example for the cycle counter or event counters to be reset). At the end + * of the exact instruction loop, zero is written to PMCR_EL0 to disable + * counting, allowing the cycle counter or event counters to be read at the + * leisure of the calling code. + */ +static void measure_instrs(int num, uint32_t pmcr) +{ + int i = (num - 1) / 2; + + assert(num >= 3 && ((num - 1) % 2 == 0)); + loop(i, pmcr); +} + +/* + * Measure cycle counts for various known instruction counts. Ensure that the + * cycle counter progresses (similar to check_cycles_increase() but with more + * instructions and using reset and stop controls). If supplied a positive, + * nonzero CPI parameter, also strictly check that every measurement matches + * it. Strict CPI checking is used to test -icount mode. + */ +static bool check_cpi(int cpi) +{ + struct pmu_data pmu = {{0}}; + + enable_counter(ARMV8_PMU_CYCLE_IDX); + set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ + + pmu.cycle_counter_reset = 1; + pmu.enable = 1; + + if (cpi > 0) + printf("Checking for CPI=%d.\n", cpi); + printf("instrs : cycles0 cycles1 ...\n"); + + for (int i = 3; i < 300; i += 32) { + int avg, sum = 0; + + printf("%d :", i); + for (int j = 0; j < NR_SAMPLES; j++) { + int cycles; + + measure_instrs(i, pmu.pmcr_el0); + cycles = get_pmccntr(); + printf(" %d", cycles); + + if (!cycles || (cpi > 0 && cycles != i * cpi)) { + printf("\n"); + return false; + } + + sum += cycles; + } + avg = sum / NR_SAMPLES; + printf(" sum=%d avg=%d avg_ipc=%d avg_cpi=%d\n", + sum, avg, i / avg, avg / i); + } + + pmu.enable = 0; + set_pmcr(pmu.pmcr_el0); + + return true; +} + +int main(int argc, char *argv[]) { + int cpi = 0; + + if (argc >= 1) + cpi = atol(argv[0]); + report_prefix_push("pmu"); report("Control register", check_pmcr()); report("Monotonically increasing cycle count", check_cycles_increase()); + report("Cycle/instruction ratio", check_cpi(cpi)); return report_summary(); }