From patchwork Tue Nov 8 18:17:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Huang X-Patchwork-Id: 9417895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7230C6022E for ; Tue, 8 Nov 2016 18:26:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66944288C3 for ; Tue, 8 Nov 2016 18:26:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B37128932; Tue, 8 Nov 2016 18:26:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EE7CB288C3 for ; Tue, 8 Nov 2016 18:26:20 +0000 (UTC) Received: from localhost ([::1]:34801 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4B6B-000749-KO for patchwork-qemu-devel@patchwork.kernel.org; Tue, 08 Nov 2016 13:26:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39213) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4Axa-0000qX-ML for qemu-devel@nongnu.org; Tue, 08 Nov 2016 13:17:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4AxW-0001oR-4u for qemu-devel@nongnu.org; Tue, 08 Nov 2016 13:17:26 -0500 Received: from mx1.redhat.com ([209.132.183.28]:52990) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4AxV-0001o8-TI for qemu-devel@nongnu.org; Tue, 08 Nov 2016 13:17:22 -0500 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BEDDF7AEA5; Tue, 8 Nov 2016 18:17:20 +0000 (UTC) Received: from weilaptop.redhat.com (vpn-58-249.rdu2.redhat.com [10.10.58.249]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uA8IHGJs031884; Tue, 8 Nov 2016 13:17:18 -0500 From: Wei Huang To: cov@codeaurora.org Date: Tue, 8 Nov 2016 12:17:13 -0600 Message-Id: <1478629035-12938-2-git-send-email-wei@redhat.com> In-Reply-To: <1478629035-12938-1-git-send-email-wei@redhat.com> References: <1478629035-12938-1-git-send-email-wei@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 08 Nov 2016 18:17:20 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v8 1/3] arm: Add PMU test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alindsay@codeaurora.org, drjones@redhat.com, kvm@vger.kernel.org, croberts@codeaurora.org, qemu-devel@nongnu.org, alistair.francis@xilinx.com, shannon.zhao@linaro.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Christopher Covington Beginning with a simple sanity check of the control register, add a unit test for the ARM Performance Monitors Unit (PMU). Signed-off-by: Christopher Covington Signed-off-by: Wei Huang Reviewed-by: Andrew Jones --- arm/Makefile.common | 3 ++- arm/pmu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++ arm/unittests.cfg | 5 ++++ 3 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 arm/pmu.c diff --git a/arm/Makefile.common b/arm/Makefile.common index ccb554d..f98f422 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -11,7 +11,8 @@ endif tests-common = \ $(TEST_DIR)/selftest.flat \ - $(TEST_DIR)/spinlock-test.flat + $(TEST_DIR)/spinlock-test.flat \ + $(TEST_DIR)/pmu.flat all: test_cases diff --git a/arm/pmu.c b/arm/pmu.c new file mode 100644 index 0000000..0b29088 --- /dev/null +++ b/arm/pmu.c @@ -0,0 +1,73 @@ +/* + * Test the ARM Performance Monitors Unit (PMU). + * + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License version 2.1 and + * only version 2.1 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License + * for more details. + */ +#include "libcflat.h" + +#define PMU_PMCR_N_SHIFT 11 +#define PMU_PMCR_N_MASK 0x1f +#define PMU_PMCR_ID_SHIFT 16 +#define PMU_PMCR_ID_MASK 0xff +#define PMU_PMCR_IMP_SHIFT 24 +#define PMU_PMCR_IMP_MASK 0xff + +#if defined(__arm__) +static inline uint32_t pmcr_read(void) +{ + uint32_t ret; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (ret)); + return ret; +} +#elif defined(__aarch64__) +static inline uint32_t pmcr_read(void) +{ + uint32_t ret; + + asm volatile("mrs %0, pmcr_el0" : "=r" (ret)); + return ret; +} +#endif + +/* + * As a simple sanity check on the PMCR_EL0, ensure the implementer field isn't + * null. Also print out a couple other interesting fields for diagnostic + * purposes. For example, as of fall 2016, QEMU TCG mode doesn't implement + * event counters and therefore reports zero event counters, but hopefully + * support for at least the instructions event will be added in the future and + * the reported number of event counters will become nonzero. + */ +static bool check_pmcr(void) +{ + uint32_t pmcr; + + pmcr = pmcr_read(); + + printf("PMU implementer: %c\n", + (pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK); + printf("Identification code: 0x%x\n", + (pmcr >> PMU_PMCR_ID_SHIFT) & PMU_PMCR_ID_MASK); + printf("Event counters: %d\n", + (pmcr >> PMU_PMCR_N_SHIFT) & PMU_PMCR_N_MASK); + + return ((pmcr >> PMU_PMCR_IMP_SHIFT) & PMU_PMCR_IMP_MASK) != 0; +} + +int main(void) +{ + report_prefix_push("pmu"); + + report("Control register", check_pmcr()); + + return report_summary(); +} diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 3f6fa45..7645180 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -54,3 +54,8 @@ file = selftest.flat smp = $MAX_SMP extra_params = -append 'smp' groups = selftest + +# Test PMU support +[pmu] +file = pmu.flat +groups = pmu