From patchwork Sun Nov 27 11:32:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cao jin X-Patchwork-Id: 9448769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D5FB60235 for ; Sun, 27 Nov 2016 11:34:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3BA0620246 for ; Sun, 27 Nov 2016 11:34:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2FB4126224; Sun, 27 Nov 2016 11:34:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BA78E20246 for ; Sun, 27 Nov 2016 11:34:55 +0000 (UTC) Received: from localhost ([::1]:53783 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cAxjS-0003je-TJ for patchwork-qemu-devel@patchwork.kernel.org; Sun, 27 Nov 2016 06:34:54 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cAxeF-0008QL-IS for qemu-devel@nongnu.org; Sun, 27 Nov 2016 06:29:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cAxeE-0000zH-Cj for qemu-devel@nongnu.org; Sun, 27 Nov 2016 06:29:31 -0500 Received: from [59.151.112.132] (port=10151 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cAxeD-0000yT-DC for qemu-devel@nongnu.org; Sun, 27 Nov 2016 06:29:30 -0500 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="13345166" Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 27 Nov 2016 19:29:15 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id 8AA7143972CE; Sun, 27 Nov 2016 19:29:12 +0800 (CST) Received: from G08FNSTD140223.g08.fujitsu.local (10.167.226.69) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 27 Nov 2016 19:29:22 +0800 From: Cao jin To: Date: Sun, 27 Nov 2016 19:32:26 +0800 Message-ID: <1480246353-10297-4-git-send-email-caoj.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1480246353-10297-1-git-send-email-caoj.fnst@cn.fujitsu.com> References: <1480246353-10297-1-git-send-email-caoj.fnst@cn.fujitsu.com> MIME-Version: 1.0 X-Originating-IP: [10.167.226.69] X-yoursite-MailScanner-ID: 8AA7143972CE.AA300 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: caoj.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v10 03/10] pcie_aer: support configurable AER capa version X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: izumi.taku@jp.fujitsu.com, alex.williamson@redhat.com, Dou Liyang , mst@redhat.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Dou Liyang Now, AER capa version is fixed to v2, if assigned device is actually v1, then this value will inconsistent between guest and host Signed-off-by: Dou Liyang Signed-off-by: Cao jin Reviewed-by: Michael S. Tsirkin --- hw/net/e1000e.c | 3 ++- hw/pci-bridge/ioh3420.c | 2 +- hw/pci-bridge/xio3130_downstream.c | 2 +- hw/pci-bridge/xio3130_upstream.c | 2 +- hw/pci/pcie_aer.c | 5 +++-- include/hw/pci/pcie_aer.h | 3 ++- 6 files changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 4994e1c..66de849 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -472,7 +472,8 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) hw_error("Failed to initialize PM capability"); } - if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) { + if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, + PCI_ERR_SIZEOF) < 0) { hw_error("Failed to initialize AER capability"); } diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index c8b5ac4..d70784c 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -135,7 +135,7 @@ static int ioh3420_initfn(PCIDevice *d) goto err_pcie_cap; } - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); + rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index cef6e13..5d1ce01 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -97,7 +97,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) goto err_pcie_cap; } - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 4ad0440..3819964 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -85,7 +85,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) pcie_cap_flr_init(d); pcie_cap_deverr_init(d); - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); if (rc < 0) { goto err; } diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 048ce6a..ac47f34 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -96,11 +96,12 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log) aer_log->log_num = 0; } -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size) +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, + uint16_t size) { PCIExpressDevice *exp; - pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, + pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver, offset, size); exp = &dev->exp; exp->aer_cap = offset; diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h index c2ee4e2..c373591 100644 --- a/include/hw/pci/pcie_aer.h +++ b/include/hw/pci/pcie_aer.h @@ -87,7 +87,8 @@ struct PCIEAERErr { extern const VMStateDescription vmstate_pcie_aer_log; -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size); +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, + uint16_t size); void pcie_aer_exit(PCIDevice *dev); void pcie_aer_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len);